Implementing Non-SDK example in SDK LPSPI (S32K144_Project_LPSPI --> SDK_S32K144_Project_LPSPI)

[KARTHKSARODE]

Hi team

As stated in the subject , Initially I explored SPI communication with sample example code "S32K144_Project_LPSPI" , where SPI communication is established between microcontroller & UJA1169TK\F

So now to get familiar with SPI SDK , I tried implementing the same with the help of SDK( PFA processor expert) 

Once after generating processor expert code , I used LPSPI_DRV_MasterTransferBlocking API to send & receive data through SPI 

uint8_t masterDataSend[2]={0xFD,0x00};
uint8_t masterDataReceive[2];

CLOCK_SYS_Init(g_clockManConfigsArr, CLOCK_MANAGER_CONFIG_CNT,
g_clockManCallbacksArr, CLOCK_MANAGER_CALLBACK_CNT);
CLOCK_SYS_UpdateConfiguration(0U, CLOCK_MANAGER_POLICY_AGREEMENT);
PINS_DRV_Init(NUM_OF_CONFIGURED_PINS, g_pin_mux_InitConfigArr);
LPSPI_DRV_MasterInit(LPSPICOM1,&lpspiCom1State,&lpspiCom1_MasterConfig0);

LPSPI_DRV_MasterTransferBlocking(LPSPICOM1,&masterDataSend[0],&masterDataReceive[0],2U,10U);

So basically I was expecting value 0xFD & 0x EF in masterDataReceive[0] and masterDataReceive[1] respectively , but I'm receiving zero in masterDataReceive[0] & [1]

To check whether the selected configuration is correct , I used normal non-sdk code to verify processor expert configuration ( Shown below)

uint16_t LPSPI1_16bits_read;

CLOCK_SYS_Init(g_clockManConfigsArr, CLOCK_MANAGER_CONFIG_CNT,
g_clockManCallbacksArr, CLOCK_MANAGER_CALLBACK_CNT);
CLOCK_SYS_UpdateConfiguration(0U, CLOCK_MANAGER_POLICY_AGREEMENT);
PINS_DRV_Init(NUM_OF_CONFIGURED_PINS, g_pin_mux_InitConfigArr);
LPSPI_DRV_MasterInit(LPSPICOM1,&lpspiCom1State,&lpspiCom1_MasterConfig0);

while((LPSPI1->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT==0);
 /* Wait for Tx FIFO available */
 LPSPI1->TDR = 0xFD00; /* Transmit data */
 LPSPI1->SR |= LPSPI_SR_TDF_MASK; /* Clear TDF flag*/
 while((LPSPI1->SR & LPSPI_SR_RDF_MASK)>>LPSPI_SR_RDF_SHIFT==0);
 /* Wait at least one RxFIFO entry */
 LPSPI1_16bits_read= LPSPI1->RDR; /* Read received data */
 LPSPI1->SR |= LPSPI_SR_RDF_MASK; /* Clear RDF flag*/

With the above code , I could see 0xFDEF in LPSPI1_16bits_read variable , from that I could conclude that there is no issue with processor expert configuration

I'm suspecting I might have sent wrong paramters for LPSPI_DRV_MasterTransferBlocking API , Please let me know if something is wrong 

[danielmartynek]

Hi @KARTHKSARODE,

Can you please read the error code that the function returns?

Have you scopped the bus?

BR, Daniel

[KARTHKSARODE]

Hi @danielmartynek 

Thanks for the response 

Function returns STATUS_SUCCESS

Sadly I don't have any scope with me to test the bus , from the code snippet can you find any error??

[danielmartynek]

Hi @KARTHKSARODE,

I don't see any issues in the code you posted.

Can you share the project so that I can reproduce it on my side?

Regards,

Daniel

[KARTHKSARODE]

Hi @danielmartynek 

After modifying from uint8_t masterDataSend[2]={0xFD,0x00} to uint8_t masterDataSend[2]={0x00,0xFD}

I'm able to receive data masterDataReceive[0]=0xEF & masterDataReceive[1]=0xFD

Why is it working for this combination , can you provide feedback on this ??

[danielmartynek]

Hi @KARTHKSARODE,

If you have a test project, please share it.

I'm not able to reproduce it.

Regards,

Daniel

[KARTHKSARODE]

HI @danielmartynek 

Please find the attached project for reference 

[danielmartynek · Accepted solution]

Hello @KARTHKSARODE,

Thank you for the project.

It depends on how the data are placed in the memory.

I get good results if I do this:

uint16_t masterDataSend[1]={0xFD00};

uint16_t masterDataReceive[1];

status=LPSPI_DRV_MasterTransferBlocking(LPSPICOM1,(uint8_t*)&masterDataSend[0],(uint8_t*)&masterDataReceive[0],2U,10U);

Regards,

Daniel

[KARTHKSARODE]

Hi @danielmartynek 

Thanks for your help