I2C related details

[vignesh3]

Hi NXP community,

In application notes  LOW period of the SCL clock should be 4.7us for standard mode. How can I configure this time delay in numbers like below picture?

And I need the details for I2C data valid delay and I2C setup hold delay, I have referred from UM10204, I did not understand properly in that, that was not much clear for me, If you give any explanation on that , It would be good?

Thank you for your reply.

[PetrS · Accepted solution]

Hi,

the timing parameters (along with equation, see Table 52-6) are described in chapter 52.3.2.4 Timing Parameters of the S32K1xx Reference manual.

Data Valid Delay (tVD;DAT) is the maximum time it takes for the data on the SDA line to become valid after a clock edge (SCL). It ensures that the receiver reads the correct data bit. In simpler terms: after the clock goes high, how long can the sender take to put valid data on SDA.

Hold Time (tHD;DAT) is the minimum time that data must remain stable after the clock line goes high. It ensures that the data is not changed too quickly after being clocked in.

BR, Petr

[vignesh3]

I am using below configuration.

I am 2sec once reading accelerometer data in polling.

The problem is after 2-3hrs it is not reading anything, I2C bus will be idle.

Can you suggest anything on this?