How to verify the clock(SPLL/SOSC) via injecting the fault so we can observe the reset

[vinay_kushwah]

Hi,

I am working on functional safety application for clock monitoring for S32K146 and I have 2 query

1. I have configured the SPLL and SOSC. As per my application, I am resetting the device incase SPLL and SOSC loss the clock happens.
SCG_SOSCCSR[SOSCCM] - System OSC Clock Monitor: I have enabled it
SCG_SOSCCSR[SOSCCMRE] - System OSC Clock Monitor Reset Enable : I have enabled it

SCG_SPLLCSR[SPLLCM] - System PLL Clock Monitor : I have enabled it
SCG_SPLLCSR[SPLLCMRE] - System PLL Clock Monitor Reset : I have enabled it

RCM_SRIE[LOL] - Loss of Lock Interrupt: I have enabled it

RCM_SRIE[LOC] - Loss of Clock Interrupt: I have enabled it

now how to inject the fault in clock (SOSC/SPLL) so that I can verify reset due to missing the clock?

2. as per the safety manual S32K1XXSM_Rev5.pdf section SM_213 Implementation hint, it is described that we can verify PLL output.

now my thinking is, if we are using below setting in EBTresos for clock configuration

SCG_SOSCCSR[SOSCCM] - System OSC Clock Monitor: I have enabled it
SCG_SOSCCSR[SOSCCMRE] - System OSC Clock Monitor Reset Enable : I have enabled it

SCG_SPLLCSR[SPLLCM] - System PLL Clock Monitor : I have enabled it
SCG_SPLLCSR[SPLLCMRE] - System PLL Clock Monitor Reset : I have enabled it

RCM_SRIE[LOL] - Loss of Lock Interrupt: I have enabled it

RCM_SRIE[LOC] - Loss of Clock Interrupt: I have enabled it

then additionally SM_213 implementation hint is not required. is my understanding correct ?

looking your feedback soon...

Thanks

[danielmartynek]

Hi,

1.

Unfortunately, there is no other method.

2.

I see you have already posted the question about SM_213 in the SafeAssureNDA community.

I will be answered there.

Thank you,

BR, Daniel

[danielmartynek]

Hi
1.
As it was discussed here:
https://community.nxp.com/t5/S32K/S32K1-How-to-test-clock-monitoring-feature-per-software/m-p/786362
You can disturb the SOSC clock externally.

2.
SM_213 is about verifying that the PLL configuration and the PLL output clock frequency is correct.
This is something different than the clock monitor.

If you have any questions regarding the safety manual.
Please post it in the SafeAssureNDA community.
https://community.nxp.com/groups/safeassure-nda

Thank you,

BR, Daniel

[vinay_kushwah]

Hi,

1. This article say that, you can manually make fault to SOSC oscillation by shorting crystal terminal to GND using a 1kohm resistor. 

https://community.nxp.com/t5/S32K/S32K1-How-to-test-clock-monitoring-feature-per-software/m-p/786362

but in my case I can not do this due to hardware limitation. do you have any other method?

2.  2rd query is not clear! 

in my understanding, the PLL input is SOSC, in case SOSC is not working properly then  with below configuration the system will get reset. further when the system is running the PLL frequency will be always correct because incase the SOSC problem occur the system will be restarted anyhow.(assuming only SOSC is main reason for PLL to get failure). 

this can be also a alternative to SM_213, is my understanding correct?

SCG_SOSCCSR[SOSCCM] - System OSC Clock Monitor: I have enabled it
SCG_SOSCCSR[SOSCCMRE] - System OSC Clock Monitor Reset Enable : I have enabled it

however I have asked for request for the safety assure NDA but there is not response yet from NXP.

also can you please take look on safety assure access request?

Thanks

@danielmartynek 

[vinay_kushwah]

I still did not get the answer in the safety community, can you please give the response..

Thanks @danielmartynek