My measurements are larger than the DS results.
yellow: wakeup key
blue: core clock
Hi @PYGC,
All specifications in Table 11 assume the clock configuration in Table 10.
Also, if you use an input active rising edge as a wakeup source, the port detects Vih_min at (0.65 x VDD), providing the input digital filter is not active.
Regards,
Daniel
Is my measuring method correct? The start is VDD * 0.65, and the end is that the core clock has output.
Hello @PYGC,
What is the frequency of the core clock?
At 48MHz, one cycle is just 20ns.
The error if measurement can be significant.
What is the background of the query?
Regards,
Daniel