How to block TXD via TXCTSE bit?

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How to block TXD via TXCTSE bit?

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Alston
Contributor II

Hi,
I'm using EVK S32K118-48 board

I want to use LPUART0 for hardware flow control,
and setting LPUART0 pinmux as follows,
PTA0 for LPUART0_CTS
PTA1 for LPUART0_RTS
PTA2 for LPUART0_RX
PTA3 for LPUART0_TX

MODIR register bit settings,
LPUART_MODIR_TXCTSSRC(0) : 0b - CTS input is the CTS_B pin.
LPUART_MODIR_TXCTSC(0) : 0b - CTS input is sampled at the start of each character.
LPUART_MODIR_TXCTSE(1) : 1b - Enables clear-to-send operation.

However, trying to use CTS to block TXD doesn't work.

Alston_0-1697094573505.png


Can you tell me how to make it work properly?

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1 Solution
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Alston
Contributor II

Hi,

you are right. Found a problem with my s32k118 evk board. I'll fix my board issues. Then close this question. Thanks.

Best Regards,

Alston

 

View solution in original post

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6 Replies
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PetrS
NXP TechSupport
NXP TechSupport

Hi,

setting looks normal. Try to check port PDIR register if pin logic level is 1, which should pause transmitting.

BR, Petr

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Alston
Contributor II

Hi Petr,

Thanks for your reply.

Let me describe it in more detail.

S32K118_IO_Signal_Description_Input_Multiplexing.xlsx :

PortCRSSSFunctionModuleDescriptionDirection
PTA0PCR_PTA00000_0110LPUART0_CTSLPUART0Clear To Send (bar)I
PTA1PCR_PTA10000_0110LPUART0_RTSLPUART0Request To SendO
PTA2PCR_PTA20000_0110LPUART0_RXLPUART0ReceiveI
PTA3PCR_PTA30000_0110LPUART0_TXLPUART0TransmitI/O

 

pin_settings_config_t g_pin_mux_InitConfigArr0[NUM_OF_CONFIGURED_PINS0] = {
    {
        .base            = PORTA,
        .pinPortIdx      = 0U,
        .pullConfig      = PORT_INTERNAL_PULL_NOT_ENABLED,
        .driveSelect     = PORT_LOW_DRIVE_STRENGTH,
        .passiveFilter   = false,
        .mux             = PORT_MUX_ALT6,
        .pinLock         = false,
        .intConfig       = PORT_DMA_INT_DISABLED,
        .clearIntFlag    = false,
        .gpioBase        = NULL,
        .digitalFilter   = false,
    },
    {
        .base            = PORTA,
        .pinPortIdx      = 1U,
        .pullConfig      = PORT_INTERNAL_PULL_NOT_ENABLED,
        .driveSelect     = PORT_LOW_DRIVE_STRENGTH,
        .passiveFilter   = false,
        .mux             = PORT_MUX_ALT6,
        .pinLock         = false,
        .intConfig       = PORT_DMA_INT_DISABLED,
        .clearIntFlag    = false,
        .gpioBase        = NULL,
        .digitalFilter   = false,
    },
    {
        .base            = PORTA,
        .pinPortIdx      = 2U,
        .pullConfig      = PORT_INTERNAL_PULL_NOT_ENABLED,
        .driveSelect     = PORT_LOW_DRIVE_STRENGTH,
        .passiveFilter   = false,
        .mux             = PORT_MUX_ALT6,
        .pinLock         = false,
        .intConfig       = PORT_DMA_INT_DISABLED,
        .clearIntFlag    = false,
        .gpioBase        = NULL,
        .digitalFilter   = false,
    },
    {
        .base            = PORTA,
        .pinPortIdx      = 3U,
        .pullConfig      = PORT_INTERNAL_PULL_NOT_ENABLED,
        .driveSelect     = PORT_LOW_DRIVE_STRENGTH,
        .passiveFilter   = false,
        .mux             = PORT_MUX_ALT6,
        .pinLock         = false,
        .intConfig       = PORT_DMA_INT_DISABLED,
        .clearIntFlag    = false,
        .gpioBase        = NULL,
        .digitalFilter   = false,
    },

...

However, the signals I see are PTA0 as output and PTA1 as input.

LPUART0->MODIR = 0x00000009

PTA->PDIR = 0x0000002E

I set TXCTSE and control PTA1(CTS), but cannot mask the PTA3(TXD) signal.

Did I miss something?

BR, Alston

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

I tried attached one and it seems to work fine.

BR, Petr

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1,467 Views
Alston
Contributor II

Hi Petr,

Thanks for your reply.

Your code works fine.

However, I tried modifying the PTB0/PTB1 pins to PTA3/PTA2
this will not work.
as follows

void PORT_init (void)
{
/*!
* Pins definitions
* ===================================================
*
* Pin number | Function
* ----------------- |------------------
* PTA2 | LPUART0 RX
* PTA3 | LPUART0 TX
*/
PCC->PCCn[PCC_PORTB_INDEX]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORT B */

PCC->PCCn[PCC_PORTA_INDEX]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORT B */
PORTA->PCR[0]|=PORT_PCR_MUX(6); /* Port A, bit 0, ALT=6: UART CTS. */
PORTA->PCR[2]|=PORT_PCR_MUX(6); /* Port A, bit 2, ALT=6: UART RX. */
PORTA->PCR[3]|=PORT_PCR_MUX(6); /* Port A, bit 3: ALT=6: UART TX. */
}

Can't PTA3/PTA2 pin be used for tx/rx?

Br, Alston

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PetrS
NXP TechSupport
NXP TechSupport

Hi, 

per IO signal table this setting would be possible, I do not expect issues here. Maybe check board schematic if signal can be measured and be on right header. But this looks normal too.

BR, Petr

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1,428 Views
Alston
Contributor II

Hi,

you are right. Found a problem with my s32k118 evk board. I'll fix my board issues. Then close this question. Thanks.

Best Regards,

Alston

 

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