How does CSEs works on S32K116LAT with security feature in case it is deactivated?

cancel
Showing results for 
Search instead for 
Did you mean: 

How does CSEs works on S32K116LAT with security feature in case it is deactivated?

204 Views
leila
Contributor III

Hi, 

 

I am using S32K116. the previews µC did not have CSEs feature but the new one has. And it is creating some trouble using the application.

SW is using whole size of FlexNVM as backup-EEEPROM and disables CSEs

FLASH_DRV_DEFlashPartition(&flashSSDConfig, 0x03, 0x08, 0x0u, false, true);

 

The problem is that if the µC is flashed for the first time with A SW, everything is fine. But if it gets erases with jLink and a B SW is flashed , it crashes on "FLASH_DRV_CommandSequence(pSSDConfig)" while executing "FLASH_DRV_DEFlashPartition".

After erasing the partitioning is gone and it seems it does not let that new B SW does the partitioning again. 

To solve this problem, I erased the µC again and flashed A SW. until now it works perfectly with A SW. Then without erasing A SW, I flashed B SW. in this way it does not need to partition FlexNVM and it works as expected.

 

Would you please explain me what the issue is here and how I could solve it? Why I am not able to flash a new SW after erasing the first on?

It seems to me eventhough CSEs is not activated, but it still does some work. It saves some key depend on the first SW "A" , and does not let any other SW to partition FlexNVM except A SW. Am I right?

 

Thank you and have a nice holidays.

 

Best regards,

Leila

0 Kudos
6 Replies

127 Views
Mohitvermaji51
Contributor I

this is really good thank you for sharing with us mybk-experience.onl mc-d.uno

192 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hi Leila,

Could you read the SIM_FCFG1_DEPART register before the B SW tries to partition it?

I don't know how you erase the A SW.

You can try the Unlock Kinetis command in J-link commander.

 

Regards,

Daniel

 

0 Kudos

184 Views
leila
Contributor III

Hi Daniel,

 

Thank you for the response.

1. I am not sure what the input to read SIM_FCFG1_DEPART is.

I tried as below:

volatile uint32_t testReadRegister = SIM_FCFG1_DEPART(0x0F);

/* Calling flash command sequence function to execute the command */
ret = FLASH_DRV_CommandSequence(pSSDConfig);

And I got testReadRegister as 0xF000.

2. I erase SW A using "J-Flash Lite" using "Erase Chip" as below. Not sure what are exact steps involved

J-Flash_Erasing.PNG

 3. Would you explain more about "You can try the Unlock Kinetis command in J-link commander." I am using S32K116 in S32 DS for ARM.

 

Thank you.

 

Best regards,

Leila

0 Kudos

176 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hi Leila,

If DEPART reads 0xF, the partitioning has been removed by the Mass Erase and the MCU can be partitioned again, so I don't think there is a problem with the erasing.

danielmartynek_0-1609604298464.png

danielmartynek_1-1609604353192.png

If I understand, there is no problem with loading the B SW either but with the execution of the Program Partition command in B SW.

Is the FLASH_DRV_CommandSequence(pSSDConfig) function is SRAM?

Which FSTAT error bits are set after the sequence?

 

Thanks,

BR, Daniel

 

 

0 Kudos

95 Views
leila
Contributor III

Hi Daniel,

 

I am sorry. My question is invalid. It ended up to be an issue with interrupts distracting partitioning.

The problem is solved by disabling interrupts while partitioning.

 

Thank you and have a nice day.

 

Best regards,

Leila

0 Kudos

132 Views
leila
Contributor III

Hi Daniel,

 

That is true. There is no problem with erasing, flashing not running SW but with partitioning for SW B.

I am using SDK RTM 3.0 and the code is as below.

I am partitioning all part as EEEPROM. (DEPART = 0x8)

I am not sure about this question. "Which FSTAT error bits are set after the sequence?"

After just calling FLASH_DRV_CommandSequence(pSSDConfig), it crashes and directly jumps into DefaultISR.

Any idea what could be the issue?

 

Best regards,

Leila

status_t FLASH_DRV_DEFlashPartition(const flash_ssd_config_t * pSSDConfig,
uint8_t uEEEDataSizeCode,
uint8_t uDEPartitionCode,
uint8_t uCSEcKeySize,
bool uSFE,
bool flexRamEnableLoadEEEData)
{
DEV_ASSERT(pSSDConfig != NULL);
DEV_ASSERT(uCSEcKeySize <= CSE_KEY_SIZE_CODE_MAX);
status_t ret; /* Return code variable */

/* Check CCIF to verify the previous command is completed */
if (0U == (FTFx_FSTAT & FTFx_FSTAT_CCIF_MASK))
{
ret = STATUS_BUSY;
}
else
{
/* Clear RDCOLERR & ACCERR & FPVIOL & MGSTAT0 flag in flash status register. Write 1 to clear */
CLEAR_FTFx_FSTAT_ERROR_BITS;

/* Passing parameter to the command */
FTFx_FCCOB0 = FTFx_PROGRAM_PARTITION;
FTFx_FCCOB1 = uCSEcKeySize;
FTFx_FCCOB2 = (uint8_t)(uSFE ? 1U : 0U);
FTFx_FCCOB3 = (uint8_t)(flexRamEnableLoadEEEData ? 0U : 1U);
FTFx_FCCOB4 = uEEEDataSizeCode;
FTFx_FCCOB5 = uDEPartitionCode;

/* Calling flash command sequence function to execute the command */
ret = FLASH_DRV_CommandSequence(pSSDConfig);
}

return ret;
}

0 Kudos