How do I set the cmu Clock in S32K324 RTD 4.0.0?

[jwkang]

When performing a Code update on S32K324 RTD 4.0.0, CMU Clcok is not generated properly. What is the correct value?

RTD is S32K3_RTD_4_0_0_P19_D2403_ASR_REL_4_7_REV_0000_20240315

[VaneB]

Hi @jwkang 

Those values correspond to the CMU_FC registers (refer to section 56.6.1 CMU_FC memory map of the S32K3xx Reference Manual, Rev. 8), For details of monitored and reference clocks refer to Clocking chapter and for module programming sequence refer to section 56.5.3.1.

Also, the usage and setting of the CMU is covered by Safety Framework (S32 Safety Software Framework (SAF) and Safety Peripheral Drivers (SPD)). There is a demo in this package.

BR, VaneB

[jwkang]

This issue occurs when running UpdateCode in RTD (generates incorrect code)
When generating code, only the content is generated without variable names.

If I remember correctly, this issue has been unresolved for a long time. RTD3.0.0 also had the same issue.

Is there a fixed RTD version?

[VaneB]

Hi @jwkang 

Could you share the configurations made in ConfigTools to verify this situation?

[jwkang]

I created a Test project for you and attached it.

Please check this project.

[VaneB]

Hi @jwkang 

I have created a new project and made the changes according to the project you posted and I can see the corresponding modification to the files according to the changes made in ConfigTools. Could you please point me to a specific situation where you see incorrect code being generated?

[jwkang]

After testing several times, the problem occurs. Have you tested it a lot?

I think it occurs when you enable Clock Register Values ​​Optimization.
And, I think the Index problem occurs when you create more than 2 Function groups of Clock.

[VaneB]

Hi @jwkang 

Since I unfortunately do not have a board with a S32K324, I did an analysis of all the RTD versions available and I could identify that the patches for version 4.0.0 do not generate all the necessary code.

If you check the S32K3XX_memory_map file attached to the reference manual you will find that all S32K3 devices have CMU 0, CMU 3, CMU 4 and CMU 5; except the K388 which are the only ones that have CMU 6.

The changes to be made are:

Clock_Ip_Cfg_Defines.h
#define CLOCK_IP_REGISTER_VALUES_COUNT       (16U)

Clock_Ip_BOARD_InitPeripherals_PBcfg.c
const Clock_Ip_RegisterValueType Mcu_aClockRegisterValues[CLOCK_IP_REGISTER_VALUES_COUNT] = {

    /*! @brief User CMU Configuration structure clock_Cfg_0 */

    {((uint32*)(IP_CMU_0_BASE + 4U)),0x000000F0U},        /* CMU_FC_0::RCCR */
    {((uint32*)(IP_CMU_0_BASE + 8U)),0x00000058U},        /* CMU_FC_0::HTCR */
    {((uint32*)(IP_CMU_0_BASE + 12U)),0x0000004AU},        /* CMU_FC_0::LTCR */
    {((uint32*)(IP_CMU_0_BASE + 20U)),0x00000000U},        /* CMU_FC_0::IER  */

    {((uint32*)(IP_CMU_3_BASE + 4U)),0x0000006EU},        /* CMU_FC_3::RCCR */
    {((uint32*)(IP_CMU_3_BASE + 8U)),0x0000015EU},        /* CMU_FC_3::HTCR */
    {((uint32*)(IP_CMU_3_BASE + 12U)),0x00000139U},        /* CMU_FC_3::LTCR */
    {((uint32*)(IP_CMU_3_BASE + 20U)),0x00000000U},        /* CMU_FC_3::IER  */

    {((uint32*)(IP_CMU_4_BASE + 4U)),0x0000008CU},        /* CMU_FC_4::RCCR */
    {((uint32*)(IP_CMU_4_BASE + 8U)),0x00000097U},        /* CMU_FC_4::HTCR */
    {((uint32*)(IP_CMU_4_BASE + 12U)),0x00000084U},        /* CMU_FC_4::LTCR */
    {((uint32*)(IP_CMU_4_BASE + 20U)),0x00000000U},        /* CMU_FC_4::IER  */

    {((uint32*)(IP_CMU_5_BASE + 4U)),0x0000008CU},        /* CMU_FC_5::RCCR */
    {((uint32*)(IP_CMU_5_BASE + 8U)),0x00000097U},        /* CMU_FC_5::HTCR */
    {((uint32*)(IP_CMU_5_BASE + 12U)),0x00000084U},        /* CMU_FC_5::LTCR */
    {((uint32*)(IP_CMU_5_BASE + 20U)),0x00000000U},        /* CMU_FC_5::IER  */

};

I have not found anything else yet.