Hi All, I have an issue in AIPS safety reaction of S32K116. We are using LPUART in DMA operation mode. Problem is usage of AIPS. My expectation is that HardFault shall ocurre when usage of LPUART is completely disabled by AIPS. Observed behavior is different. Processor still works without call HardFault exception. Only DMA does not work properly. I am not able to find successful explanation of that. I can send complete register setting of the processor. I guess, there should be an explanation in processor architecture. For example DMA like a master is not controlled by AIPS. MPRA register is not described well in reference manual. Only three masters are there but nowhere is described what is what. I expect that 0 is core 1 is debugger and 2 is DMA. But this register is only setting of access into AIPS, not for LPUART periphery. Does somebody knows why HardFault is not called when LPUART is blocked by AIPS and DMA try to write something into its?
Hi @SafetyRedneck,
Hard_Fault is an exception of the core, it rises when the core detect a bus error, for example.
But if you disable the access of eDMA to a peripheral, for example, LPUART0:
the eDMA should detect an error, e.g DMA_ES[DBE] (Destination Bus Error, the most-recently recorded error was a bus error on a destination write).
Regards,
Daniel
Hello DanielMartynek
Thank you for reply. I can say now where is the problem. The HardFault interrupt is not caused by AIPS periphery but by Master M0 (core). AIPS only block access into specific periphery. Similar situation is for DMA. The DMA is master M2. Its reaction is not HardFault interrupt but DMA Error interrupt. I have solution now. I have to add DMA error interrupt routine with expected safe reaction. Of course I have to also rework design and SW architecture
Thank you for help.
Best regards