HSE PLL configuration

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HSE PLL configuration

1,330 Views
DGB
Contributor II

Hello, I'm using S32K312 micro in the project. During evaluation of AES CMAC generation/verification on 1mb of data by HSE it turn out that the time of this operation is not acceptable - too long. After analysis of RM it seems that it shall be possible to speed up this operation by enabling PLL for HSE clock, but it's not straight forward mention how to do this, and I would like to not brick my board for any reason.

My current status is following:

- HSE FW was installed on the board without IVT.

- UTEST FW EN (0x1B000000) flag is set.

What else should be configured in order to enable PLL for HSE to speed up the clock? I was able to determine that in addition to above, Crystal oscillator configuration flag (0x1B000050) has to be enabled, but are there any other dependencies which shall be configured?

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lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi @DGB 

To enable the FXOSC and PLL in this way is useful when it is required to make the secure boot faster. In fact, PLL_ENABLE in Boot Configuration Word has effect only if secure boot is enabled - when BOOT_SEQ = 1.
If you do not need this, it is sufficient to configure the clock in your application. In case of S32K312, you can use configuration HSE_CLK = 120MHz and CORE_CLK = 120MHz (this is called "Option B" in HSE and S32K3 manuals).
By default, the HSE runs from FIRC clock, so make sure that HSE_CLK is configured to 120MHz:

lukaszadrapa_0-1687355479726.png

 

lukaszadrapa_1-1687355485265.png

 

And then here's what you can expect:

lukaszadrapa_2-1687355495235.png

 

If you want to enable the PLL at boot time, it is sufficient to program 0x1B000050 accordingly. This is a screenshot from secure boot application note (you can find it in Secure Files section on S32K3 main page):

lukaszadrapa_3-1687355508688.png

 

Regards,

Lukas

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wuxianlong
Contributor III

@lukaszadrapa 

What is the configuration format of this FXOSC clock? look at your screenshot and write UTEST as 0xC9D0 3E80 AAAA 5555. It looks like a 32-bit little-endian , but write 2 bytes at a time.

BRs,
xianlong

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1,279 Views
DGB
Contributor II

Hi Lucas thank you very much for the answer. Seems that I was using already PLL but HSE_CLK was set to 60MHz with divider equal 1. After changing to 120MHz and divider to 0, I don't get any response from HSE, only timeouts. Is there something in addition which I should do?

 

I addition I was able to determine that after changing HSE_CLK to 120MHz, apparently HSE FW was removed from my board, I believe by SBAF since address 0x4038C107 value is 0. When I tried to install FW one more time (without IVT), again it was removed after installation during boot stage, seems it might be related with "HSE Firmware Handshake" functionality. Do you have any guides how to distinguish what is wrong? I'm using following FW: s32k3x2_hse_fw_0.13.0_2.6.0_pb221129.bin.pink.

EDIT:

I was able to determine that if I change HSE_CLK to 120MHz, I'm receiving HSE_SWT_RST, and at the end HSE FW is erased. When I change back to 60MHz for HSE_CLK, HSE work properly. So at the end I'm changing only divider for HSE_CLK and it's making huge difference in behavior. Do you have any idea what could be wrong, or what I should check?

Other bits in MC_RGM (HSE_CLK_FAIL, HSE_TMPR_RST, HSE_BOOT_RST, JTAG_RST) related with HSE are set to 0 for 120MHz HSE_CLK, only this HSE_SWT_RST is triggered to 1.

 

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1,232 Views
lukaszadrapa
NXP TechSupport
NXP TechSupport

I found that one more thing is necessary:

lukaszadrapa_0-1687529635608.png

 For Option B, it is necessary to program the dcf_client_utest_misc as mentioned in the screenshot.

lukaszadrapa_1-1687529725017.png

 HSE_CLK_MODE_AND_GSKT_CTRL needs to be 10 or 11.

 

Then also double check if all your clocks meets requirements listed in the Table 144 in the RM.

Similar issues are usually caused by wrong clock settings, so I believe this will solve the problem.

If it helps, attached is sample project which shows how to modify the dcf_client_utest_misc. You just need to port this to S32K312, check first available position in the UTEST and program the DCF accordingly. Notice that it is OTP area.

Regards,

Lukas

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1,194 Views
DGB
Contributor II

Hi, after configuration of DCF record for UTEST_MISC still I'm observing same issue, but I'm not sure if it's taken into account by MICRO. In memory it looks in following way:

DGB_1-1687785297953.png

but in register DCMROF21 still I can observed 0 for HSE_CLK_MODE_OPTION

DGB_2-1687785357064.png

Is there any other register which shall be set in order to eg. DCF record configuration was taken into account?

Since I'm using different toolchain (compiler) I wasn't able to run sample app which you provide, but I used debugger to program DCF record directly from binary, and seems it was done currently. Do you have any idea why my DCF record configuration is not taken into account?

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lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi @DGB 

I just got new information. This configuration of HSE_CLK_MODE in DCF record (and also configuration of FXOSC) has no effect unless PLL_ENABLE in IVT is enabled. SBAF will ignore it and FIRC will be used at boot time. And PLL_ENABLE has effect only when BOOT_SEQ is 1 (i.e. secure boot enabled).
I'm sorry, I provided wrong information in previous post. The documentation is little bit confusing here, I will ask to clarify it.

Based on HSE_CLK_MODE_OPTION (if PLL_ENABLE is set), SBAF configures MUX_0_DC_1 and MUX_0_DC_2 dividers. If PLL_ENABLE is not used, it's up to user to configure these dividers later in the code. So, we are getting back to Table 144 in the S32K3 RM. Could you send me your clock configuration? Is it the same as in Table 144?

Regards,

Lukas

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wuxianlong
Contributor III

Hi@lukaszadrapa 

Based on HSE_CLK_MODE_OPTION (if PLL_ENABLE is set), SBAF configures MUX_0_DC_1 and MUX_0_DC_2 dividers. 

If my FXOSC is 40MHz, how should I configure MUX_0_DC_1 and MUX_0_DC_2 , SBAF will automatically adjust? 

BRs,
xianlong

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1,147 Views
DGB
Contributor II

Hi, from my point of view clocks are configured accordingly, I send configuration in separate NXP ticket.

In addition as I mentioned for HSE_CLK == 60Mhz (div is set), the HSE is working correctly (I can perform HSE jobs and get the version etc.), but when I remove div for HSE_CLK to have 120Mhz then mentioned issue is observed (SBAF removes HSE FW since most probably handshake fails). Today I even updated SBAF successfully on HSE_CLK == 60Mhz to have compliant version to HSE FW, but again when I changed HSE_CLK divider to have 120Mhz issue still is observed.

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Yiming2
Contributor II

hello, I also met the same problem. When I set the HSE_CLK=120MHz the reset is happened and HSE FW can not properly work. But It can correctly worked in case of HSE_CLK=60M Hz. So cloud you tell me how to fix this problem?

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wuxianlong
Contributor III
You can modify the DCF to solve this problem, which is mentioned above. NXP's S32K312 installation routine is also implemented in code. S32K312_HSE_FW_INSTALL_V_0_1_2_1
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