For FLEXCAN, I use the receive interrupt enable, but send interrupt disabled, how to operate?

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For FLEXCAN, I use the receive interrupt enable, but send interrupt disabled, how to operate?

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jia_xuan
Contributor I

For FLEXCAN, I use the receive interrupt enable, but send interrupt disabled, how to operate?

When I transmission the data, I do not want to trigger an interrupt。

Please help me.

Thank you.

Best Regards.

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3 Replies

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AnaAldescu
NXP Employee
NXP Employee

Hello,

Could you please provide more details about your use case? As for my understanding, do you need to disable interrupts when transmitting data and keep them enabled only for receiving data?

Regards,

Ana

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jia_xuan
Contributor I

Yes, I want to receive data when the interrupt is triggered, but when sending data does not trigger the interrupt.

I tried to add NVIC_DisableIRQ(CAN0_ORed_0_15_MB_IRQn) and NVIC_EnableIRQ(CAN0_ORed_0_15_MB_IRQn) at the beginning and end of the send function, but did not succeed.

#define TX_MAILBOX (8UL)
#define RX_MAILBOX (0UL)
void SendCANData(uint32_t mailbox, uint32_t messageId, uint8_t * data, uint32_t len)
{
    //NVIC_DisableIRQ(CAN0_ORed_0_15_MB_IRQn);
    flexcan_data_info_t dataInfo =
   {
    .data_length = len,
    .msg_id_type = FLEXCAN_MSG_ID_EXT,
    .enable_brs = false,
    .fd_enable = false,
    .fd_padding = 0U
    };
    FLEXCAN_DRV_ConfigTxMb(INST_CANCOM1, mailbox, &dataInfo, messageId);
    FLEXCAN_DRV_Send(INST_CANCOM1, mailbox, &dataInfo, messageId, data);
    //NVIC_EnableIRQ(CAN0_ORed_0_15_MB_IRQn);
}

/*Interrupt callback function*/

void HAL_CAN0_Callback(void) 

    if( (recvBuff.msgId == 1)
    {
     InsertCanQueue(recvBuff);
    }  

}

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

The Message Buffer interrupt is enabled if respective bit in IMASK1 register is set. Then if flag is set in the IFLAG1 register the interrupt is called. The flag is cleared by writing 1 to respective bit in the IFLAG1.

If you do not want to have interrupt generated after successful message transmission, then clear respective bit in IMASK1 register.

BR, Petr