Flash/CPU error on S32K1xx

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Flash/CPU error on S32K1xx

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sero
Contributor II

Hello Together,

i have some problems with a S32K142

I was able to debug and flash the device for quite some time.

Now, after i had some connection problems, i can still connect to the Debug-Interface (via Segger Jlink) but it tells me that the either CPU cannot be halted or that the device is in permanent reset .
After connecting the reset-pin to GND and another access via Jlink, I tried to unlock the device (which was successful).

After this, i can - sometimes - access the memory, but it keeps changing the content which is shown.

erase/flash/etc. is not possible

I tried SWD and JTAG, i also changed the speed.

As far as i can see from the datasheet, the device cannot start the internal RC Oscillator to provide a clock to the CPU and the memory.

To give some more hint: because i had an error in the design, i provided a signal on a pin before i had a power connected. I resolved the problem, so this was not happening any more at the time the above error occured.

Is it possible that i ruined the port or the oscillator unit with the "supply via ESD Diode"?

It doesn't seem that i had a latch-up because the ports still worked fine (and the connection via SWD/JTAG is still possible).

Thanks for your help

Roland

 

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sero
Contributor II

But it seems i found the answer in the document you shared.

Page 7, on top:

Applying voltages to I/O pins when the processor is not powered. If the pin’s voltage level electrical specifications are violated,the processor can attempt a partial power up and/or puts the flash into an undefined state. This can lead to corruption of flashcontents, corruption of flash control logic, or corruption of device configuration and trim values which in turn can lead to theprocessor reporting as secured (locked device) or failure of the processor to respond to and complete flash commands

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Omar_Anguiano
NXP TechSupport
NXP TechSupport

Hello

I agree, the 5V applied to the GPIO while the device was powered off might cause damage to your device.
I apologize for the inconvenience this may cause you, if you have more questions do not hesitate to ask me.

Best regards,
Omar

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sero
Contributor II

After you read the jflash messages, do you find any chance to connect to the processor core/flash?

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sero
Contributor II

Good Morning Omar,

i applied 5V (from a switch) to a GPIO, while the processor did not had a power supply. Because of it I had erratic behaviour (like GPIO toggling, PLL not working, ..)

After I found out, I connected the switch via a transfer gate powered by the processors power supply.


After some flashing and debugging i was not able to connect any more. I don't use the protection flash addresses in my code.

Here is the jlink transceipt.


Connecting to target via JTAG
InitTarget() start
InitTarget()
TotalIRLen = 4, IRPrint = 0x01
JTAG chain detection found 1 devices:
#0 Id: 0x0993801D, IRLen: 04, JTAG-DP
InitTarget() end
TotalIRLen = 4, IRPrint = 0x01
JTAG chain detection found 1 devices:
#0 Id: 0x0993801D, IRLen: 04, JTAG-DP
DPv0 detected
Scanning AP map to find all available APs
AP[2]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x24770011)
AP[1]: JTAG-AP (IDR: 0x001C0000)
Iterating through AP map to find AHB-AP to use
AP[0]: Skipped. Invalid implementer code read from CPUIDVal[31:24] = 0xFF
AP[1]: Skipped. Not an AHB-AP
DPv0 detected
Scanning AP map to find all available APs
AP[2]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x24770011)
AP[1]: JTAG-AP (IDR: 0x001C0000)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Found Cortex-M4 r0p1, Little endian.
FPUnit: 6 code (BP) slots and 2 literal slots
CoreSight components:
ROMTbl[0] @ E00FF000
Initializing 28672 bytes work RAM @ 0x1FFFC000
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
Reset: Core did not halt after reset, trying to disable WDT.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
Reset: CPU did not halt after reset.
Reset: Using fallback: Reset pin.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via reset pin
T-bit of XPSR is 0 but should be 1. Changed to 1.
Cortex-M4 identified.
J-Link>

here after i tried the "unlock kinetis" command

J-Link>unlock kinetis
Found SWD-DP with ID 0x2BA01477
Unlocking device...O.K.
J-Link>unlock kinetis
Found SWD-DP with ID 0x2BA01477
Unlocking device...O.K.
J-Link>unlock kinetis
Found SWD-DP with ID 0x2BA01477
Unlocking device...O.K.
J-Link>unlock kinetis
Found SWD-DP with ID 0x2BA01477
Unlocking device...O.K.

J-Link>r

InitTarget() start
InitTarget()
Device will be unsecured now.
InitTarget() end
Found SW-DP with ID 0x2BA01477
DPv0 detected
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Found Cortex-M4 r0p1, Little endian.
FPUnit: 6 code (BP) slots and 2 literal slots
CoreSight components:
ROMTbl[0] @ E00FF000
Reset delay: 0 ms
Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
Reset: S_RESET_ST never gets cleared. CPU seems to be kept in reset forever.
Reset: Using fallback: Reset pin.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via reset pin
Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Reset: Reconnecting and manually halting CPU.
Found SW-DP with ID 0x2BA01477
DPv0 detected
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Found Cortex-M4 r0p1, Little endian.
CPU could not be halted
Reset: Core did not halt after reset, trying to disable WDT.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via reset pin
T-bit of XPSR is 0 but should be 1. Changed to 1.
J-Link>

using SWD won't make a difference.

From time to time i get different behaviours, and sometimes i can read memory content. But the content changes every time i read it out.Sadly i cannot reproduce this right now but i keep trying.

 

 

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Omar_Anguiano
NXP TechSupport
NXP TechSupport

Hello sero

For all reset sources, the RESET_B pin is driven low by the MCU for at least 128 bus clock cycles and until flash memory initialization has completed.
After flash memory initialization has completed, the RESET_B pin is released and the internal chip reset de-asserts. Keeping the RESET_B pin asserted externally delays the negation of the internal chip reset.

It could be helpful if you share with me the details of the error you had in design, also the details of the error messages could help a lot.

 This behavior could be caused because the flash got corrupted, the MCU is lockup by the Flash protection mechanism. To avoid wrong flash functionality the MCU is in a permanent reset state. Please take a look at AN12130 for more information about how to prevent this issue happen. Unfortunately, we have not scripts to recover MCU from that state. https://www.nxp.com/docs/en/application-note/AN12130.pdf

 

I'm looking foward to your reply, if you have more questions do not hesitate to ask me.
Best regards,
Omar

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