FXOSC configuration on demoboard S32K311-EVB Q100

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FXOSC configuration on demoboard S32K311-EVB Q100

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AsmId
Contributor III

Dear NXP community,

I would like to know which value should I set for the two parameters EOCV and GM_SEL when initializing the FXOSC with the NXP demoboard S32K311-EVB Q100.

The issue that I encounter is that when I let the previous parameters with the reset values, it seems that the FXOSC or the PLL goes in overclocking and the SW stop functionning.

Thank you for the support.

Best regards,

 

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Robin_Shen
NXP TechSupport
NXP TechSupport

Hi

The default value should not cause the PLL to be overclocked.

Could you share the S32DS version you are using and also the RTD version? 

Did you configure Clock Configuration Tool according to the S32K3XXRM Table 151. Option B - Reduced Speed mode (CORE_CLK @ 120 MHz) by refer to S32K3xx Pins and Clocks with RTD - Training?

Note the ratio between APIS_SLOW_CLK and HSE_CLK should be 1:2 by default. For more detail, please refer to the discussion in https://community.nxp.com/t5/S32K/If-I-don-t-give-s32k312-delay-the-CAN-stop-during-operation/m-p/18...


Best Regards,
Robin
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Robin_Shen
NXP TechSupport
NXP TechSupport

Hi

The default value should not cause the PLL to be overclocked.

Could you share the S32DS version you are using and also the RTD version? 

Did you configure Clock Configuration Tool according to the S32K3XXRM Table 151. Option B - Reduced Speed mode (CORE_CLK @ 120 MHz) by refer to S32K3xx Pins and Clocks with RTD - Training?

Note the ratio between APIS_SLOW_CLK and HSE_CLK should be 1:2 by default. For more detail, please refer to the discussion in https://community.nxp.com/t5/S32K/If-I-don-t-give-s32k312-delay-the-CAN-stop-during-operation/m-p/18...


Best Regards,
Robin
-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
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AsmId
Contributor III
Hi @Robin_Shen,
It seems that the issue was due indeed to the ratio between AIPS_SLOW_CLK and HSE_CLK, I had a ratio of 1:4, so I changed it to 1:2 and that solved the problem.
Thank you for the support.
Best Regards,
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