Hello Kaihao,
Good job !
So what kind of interrupt do you use ? Counter overflow or FTM Channel interrupt ? I used FTM2_QD to measure every rising or falling edge of A and B by using counter overflow interrupt. But I am still troubled by the interrupt configuration.
Below is my configuration for FTM2_QD. Please provide some help. Thanks. By the way, my Wechat ID is cjf715822 and email address is cjf6221@gmail.com.
void FTM2_Quadrature_Decoder_Mode()
{
/* Enable clock for PORTD */
PCC->PCCn[PCC_PORTD_INDEX] = PCC_PCCn_CGC_MASK;
/* Select and enable clock for FTM2 */
PCC->PCCn[PCC_FLEXTMR2_INDEX] = PCC_PCCn_PCS(6) | PCC_PCCn_CGC_MASK;
PORTD->PCR[10] = PORT_PCR_MUX(3); // Set PTD10 for FTM2 - Phase B input
PORTD->PCR[11] = PORT_PCR_MUX(3); // Set PTD11 for FTM2 - Phase A input
FSL_NVIC->ISER[FTM2_IRQn / 32] |= (1 << (FTM2_IRQn % 32)); // Enable FTM2 counter overflow interrupt
// FSL_NVIC->ICPR[116/32] = 1 << (116% 32);
FSL_NVIC->ISER[116/32] = 1 << (116% 32);
// FSL_NVIC->IP[116] = 0;
FTM2->MODE = FTM_MODE_WPDIS_MASK | FTM_MODE_INIT_MASK | FTM_MODE_FTMEN_MASK;
//Enable FTM2 module (0x00000005): D2(WPDIS) and D0(FTMEN) are set.
FTM2->MOD = FTM_MOD_MOD(4096); // overflow after totally 4096 rising/falling edges
FTM2->CNT = 0;
FTM2->CNTIN = FTM_CNTIN_INIT(0);
// FTM2->QDCTRL= FTM_QDCTRL_QUADEN_MASK; // Enable QD mode
FTM2->QDCTRL= 0x000000C1; // Enable QD mode and input filter mode
FTM2->SC |= FTM_SC_CLKS(1) | FTM_SC_PS(2) | FTM_SC_CPWMS_MASK | FTM_SC_TOIE_MASK;
// FTM_SC_CLKS(1): select FTM as input timer.
// FTM_SC_PS(2): clock source FTM, prescaler 2^2, clock frequency = 112MHz/4 = 28MHz
// FTM_SC_TOIE_MASK: enable timer overflow interruption
// FTM_SC_CPWMS_MASK; D5(CPWMS) is set to enable up-down counting mode
}
Below is the overflow interrupt function.
void FTM2_Ovf_Reload_IRQHandler()
{
PTC->PTOR |= 1<<9; // Toggle PTC9 for scope display
FTM2_ISR_Counter++;
Temp_EncoderB = FTM2->CONTROLS[0].CnV; //store the captured C0V value (Counter's vaule)
Temp_EncoderA = FTM2->CONTROLS[1].CnV; //store the captured C1V value (Counter's vaule)
FTM2->CONTROLS[0].CnSC &= ~FTM_CnSC_CHF_MASK; //clear Ch0 flag D7(CHF) is required to be reset after reading
FTM2->CONTROLS[1].CnSC &= ~FTM_CnSC_CHF_MASK; //clear Ch1 flag D7(CHF) is required to be reset after reading
Count_Encoder = FTM2->CNT;
FTM2->SC &= ~FTM_SC_TOF_MASK; // Clear timer overflow flag D9(TOF) is reset
