ERROR with ADC triggering by FTM and PDB modules

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ERROR with ADC triggering by FTM and PDB modules

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1090097669
Contributor III

Hello All,

Recently, I was debugging the issue of FTM triggering ADC sampling, using FTM3 to trigger ADC1 and PDB1. The current problem is that there is an output of FTM3, but neither PDB1 nor ADC1 is triggered.

The following are my configuration items:

1090097669_0-1606718828081.png1090097669_1-1606718846385.png

And Where is the configuration problem or missing configuration items?

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

 

try to refer to simple S32DS "S32K144_Project_PDB" example. It configures PDB for continuous mode SW triggered, but you can test if ADC interrupt is correctly entered with configured period.

Or share your code, so we can test it.

 

BR, Petr

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

 

you should also route FTM trigger (init_trig or ext_trig) into PDB1 input using TRGMUX. Use 

TRGMUX->TRGMUXn[TRGMUX_PDB1_INDEX] |= TRGMUX_TRGMUXn_SEL0(28); // use FTM3_INIT_TRIG as PDB1 HW trigger

FTM output trigger should be also enable within FTM External Trigger (EXTTRIG) register.

 

BR, Petr

 

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2,771 Views
1090097669
Contributor III

hello PetrS,

It has been able to trigger the sampling interrupt of ADC, but the period of entering the interrupt is different from what I expected, which is much smaller than the expected period

 
 
 

/* SW=3, TRGMUX initialization to route FTM Init trigger signal into PDB0 trigger input */
void TRGMUX_Init()
{
//PCC->PCCn[PCC_TRGMUX_INDEX] = PCC_PCCn_CGC_MASK; // Enable clock for TRGMUX module
TRGMUX->TRGMUXn[TRGMUX_PDB1_INDEX] = TRGMUX_TRGMUXn_SEL0(0x1D); // Set FTM3 as a trigger source for PDB0
}

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

 

what is an expected period and the one you have?
Do you read ADC Data result register within ADC interrupt so COCO flag is cleared?

 

BR, Petr

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2,732 Views
1090097669
Contributor III

Morning,

The interrupt cycle of my PDB is correct, which is 80kHz. Theoretically, my ADC interrupt cycle should also be 80kHZ, but according to the current test data, the ADC interrupt cycle is 400kHZ. In addition, I read the data register in the ADC interrupt

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

 

try to refer to simple S32DS "S32K144_Project_PDB" example. It configures PDB for continuous mode SW triggered, but you can test if ADC interrupt is correctly entered with configured period.

Or share your code, so we can test it.

 

BR, Petr

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