Does the gPTP protocol stack of the S32K3 enable the HSE module?

[FrankLiu2019]

After I downloaded the gPTP demo for the s32k3 onto the chip, I was unable to connect to the chip again using JLink's jflash. The log indicated "HSE firmware detected","Could not read CPUID register". How can I reconnect to the chip and disable the HSE function in the demo?Is HSE the reason why I can't connect to the chip?

When I connect using the JTAG interface, sometimes jflash asks me to input the ID Code like this NXP S32K3xx - SEGGER Knowledge Base

My operating environment is 

• S32 Design studio 3.6.0 (Updated to 3.6.2) with NXP GCC 10.2.0; Version 1728; Build
id: 202307190908
• S32K3xx Development package 3.6.2 (part of Design Studio 3.6.2)
• S32K3xx RTD 6.0.0 (SW32K3_S32M27x_RTD_R21-11_6.0.0_D2506)
• Optional for FreeRTOS example applications S32K3 FreeRTOS 5.0.0
(SW32K3_FreeRTOS_11.1.0_5.0.0_CD1_D2409)

• SW32K3xx_M7_gPTP_1.0.0_D2507

The normal connection log of jflash is

Connecting ...
- Connecting via USB to probe/ programmer device 0
- Probe/ Programmer firmware: J-Link V11 compiled Apr 27 2041 16:36:21
- Probe/ Programmer S/N: *********
- Device "S32K344" selected.
- Target interface speed: 500 kHz (Fixed)
- VTarget = 3.185V
- ConfigTargetSettings() start
- ConfigTargetSettings() end - Took 12us
- InitTarget() start
- SDA_AP detected
- Unlocking device if necessary...
- Device is not locked. Proceeding without the unlock procedure.
- Checking if debug access is already enabled...
- Debug access is not enabled yet. Performing enable debug access sequence...
- Debug access enabled
- Checking if HSE firmware is installed...
- HSE firmware not installed
- Checking if Cortex-M7_0 and Cortex-M7_1 are operating in lockstep mode
- Lock step mode enabled
- InitTarget() end - Took 16.0ms
- Found SW-DP with ID 0x6BA02477
- DPIDR: 0x6BA02477
- CoreSight SoC-400 or earlier
- AP map detection skipped. Manually configured AP map found.
- AP[0]: MEM-AP (IDR: Not set, ADDR: 0x00000000)
- AP[1]: APB-AP (IDR: Not set, ADDR: 0x00000000)
- AP[2]: MEM-AP (IDR: Not set, ADDR: 0x00000000)
- AP[3]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
- AP[4]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
- AP[5]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
- AP[6]: MEM-AP (IDR: Not set, ADDR: 0x00000000)
- AP[7]: MEM-AP (IDR: Not set, ADDR: 0x00000000)
- AP[4]: Skipped ROMBASE read. CoreBaseAddr manually set by user
- AP[4]: Core found
- CPUID register: 0x411FC272. Implementer code: 0x41 (ARM)
- Cache: L1 I/D-cache present
- Found Cortex-M7 r1p2, Little endian.
- FPUnit: 8 code (BP) slots and 0 literal slots
- ROM table scan skipped. CoreBaseAddr manually set by user: 0x40250400
- I-Cache L1: 8 KB, 128 Sets, 32 Bytes/Line, 2-Way
- D-Cache L1: 8 KB, 64 Sets, 32 Bytes/Line, 4-Way
- SetupTarget() start
- Initializing ECC RAM...
- RAMCodeAddr: 0x20000000
- RAMInitAddr: 0x20000010
- RAMInitSize: 0x00007FF0
- InitPattern: 0xDEADBEEF
- ECC RAM initialized successfully
- Initializing ECC RAM...
- RAMCodeAddr: 0x20000000
- RAMInitAddr: 0x20400000
- RAMInitSize: 0x00004000
- InitPattern: 0xDEADBEEF
- ECC RAM initialized successfully
- SetupTarget() end - Took 53.8ms
- Executing init sequence ...
- Initialized successfully
- Target interface speed: 1000 kHz (Fixed)
- Found 1 JTAG device. Core ID: 0x6BA02477 (None)
- Connected successfully

The abnormal connection Jflash log is

Connecting ...
- Connecting via USB to probe/ programmer device 0
- Probe/ Programmer firmware: J-Link V11 compiled Apr 27 2041 16:36:21
- Probe/ Programmer S/N: *********
- Device "S32K344" selected.
- Target interface speed: 500 kHz (Fixed)
- VTarget = 3.225V
- ConfigTargetSettings() start
- ConfigTargetSettings() end - Took 9us
- InitTarget() start
- Unknown SDA AP Id detected: 0x00000000
- InitTarget() end - Took 3.05ms
- ConfigTargetSettings() start
- ConfigTargetSettings() end - Took 18us
- InitTarget() start
- SDA_AP detected
- Unlocking device if necessary...
- Device is not locked. Proceeding without the unlock procedure.
- Checking if debug access is already enabled...
- Debug access is not enabled yet. Performing enable debug access sequence...
- Debug access enabled
- Checking if HSE firmware is installed...
- HSE firmware detected (SWAP enabled)
- Checking if Cortex-M7_0 and Cortex-M7_1 are operating in lockstep mode
- Lock step mode enabled
- InitTarget() end - Took 19.8ms
- Found SW-DP with ID 0x6BA02477
- DPIDR: 0x6BA02477
- CoreSight SoC-400 or earlier
- AP map detection skipped. Manually configured AP map found.
- AP[0]: MEM-AP (IDR: Not set, ADDR: 0x00000000)
- AP[1]: APB-AP (IDR: Not set, ADDR: 0x00000000)
- AP[2]: MEM-AP (IDR: Not set, ADDR: 0x00000000)
- AP[3]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
- AP[4]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
- AP[5]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
- AP[6]: MEM-AP (IDR: Not set, ADDR: 0x00000000)
- AP[7]: MEM-AP (IDR: Not set, ADDR: 0x00000000)
- AP[4]: Skipped ROMBASE read. CoreBaseAddr manually set by user
- AP[4]: Skipped. Could not read CPUID register
- Attach to CPU failed. Executing connect under reset.
- DPIDR: 0x6BA02477
- CoreSight SoC-400 or earlier
- AP map detection skipped. Manually configured AP map found.
- AP[0]: MEM-AP (IDR: Not set, ADDR: 0x00000000)
- AP[1]: APB-AP (IDR: Not set, ADDR: 0x00000000)
- AP[2]: MEM-AP (IDR: Not set, ADDR: 0x00000000)
- AP[3]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
- AP[4]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
- AP[5]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
- AP[6]: MEM-AP (IDR: Not set, ADDR: 0x00000000)
- AP[7]: MEM-AP (IDR: Not set, ADDR: 0x00000000)
- AP[4]: Skipped ROMBASE read. CoreBaseAddr manually set by user
- AP[4]: Skipped. Could not read CPUID register
- Could not find core in Coresight setup
- ERROR: Failed to connect.
Could not establish a connection to target.
- ERROR: Connect failed

[davidtosenovjan]

I don't think gPTP demo has anything to do with HSE.

Your log message says:
- Checking if HSE firmware is installed...
- HSE firmware detected (SWAP enabled)

what may actually mean only that HSE FW is installed and HSE memory layout for A/B swap is applied. Was used HSE on this board?

[FrankLiu2019]

Thank you for your reply. I have never used HSE on this board. This is a new board. I downloaded the lighting demo and it worked properly. I was able to reconnect the JTAG and erase the program. Then I downloaded gPTP demo 1.0. After that, I was no longer able to connect to the chip or erase the program. I'm not familiar with gPTP. Was there any restriction on JTAG in the demo? Or perhaps it's a problem with the jflash software from Segger?

[davidtosenovjan]

Do you see RESET led lighting?

[FrankLiu2019]

I don't understand what you mean. My board was developed by myself. On this board, I ran other normal programs. There was no reset indicator light on the board.I modified the clock and EMAC pins based on the gPTP demo. After downloading it, by observing the current, I found that the program did not reset.

[davidtosenovjan]

In this case I would recommend to measure RESET signal by scope to know whether device stays in reset or not.

[FrankLiu2019]

I have captured the waveform of the reset pin using the oscilloscope. The chip is indeed undergoing periodic reset. When I disable the SXOSC, the period is 8 ms. When I enable the SXOSC, the period is 5 ms.Do you have any ideas?

[davidtosenovjan · Accepted solution]

S32K3 have reset escalation feature, what means after certain amount of functional resets, destructive reset is issued and after certain amount of destructive resets, MCU stays in reset to next POR. So if functional reset is periodically issued for whatever reason (watchdog for instance or some misconfiguration of clock or similar reason), it may lead to having MCU in reset because of code executed after POR from internal flash.
Solution can be to stop the device immediately after POR and erase code flash memory content.

Here there is a solution for J-link (I have personally no experience with):
https://community.nxp.com/t5/S32-SDK/failed-to-power-up-dap-after-program-s32k312-with-pll0-equal/m-...

Hope it helps

[FrankLiu2019]

Hi david

What you said is exactly the problem I'm facing.

I tried the method you suggested, but it didn't work. Forget about it for now. Another question I have is whether it's possible to disable this function of the S32K3.?I tried to deactivate it in the S32DS, and it seemed to work. Is this operation correct?

Based on the gPTP demo, I disabled Func_Threshold_Reset and changed MCU_PRECOMPILE_SUPPORT from STD_ON to STD_OFF,Then the code can be run.I still don't know what caused the reset at present.

[davidtosenovjan]

Yes, correct

[FrankLiu2019]

How can I obtain the Debug Authentication ID code? I urgently need to know how to remove this restriction on JTAG. Dear employees of NXP, could you please help me? @VaneB