DWT on S32K11x

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DWT on S32K11x

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Catosh
Contributor IV

Hi all, 

according to the safety manual, 

pastedImage_1.png

Various points here:

I defined on my application the dwt type (wasn't present on S32K11x .h file)

#define DWT_NUMCOMP_VALUE 2u

typedef struct {
__I uint32_t CTRL;
//__I uint32_t RESERVED0[6]; //TODO: this can be changed.
volatile uint32_t CYCCNT;
volatile uint32_t CPICNT;
volatile uint32_t EXCCNT;
volatile uint32_t SLEEPCNT;
volatile uint32_t LSUCNT;
volatile uint32_t FOLDCNT;
__I uint32_t PCSR;
struct {
__IO uint32_t COMP;
__IO uint32_t MASK;
__IO uint32_t FUNCTION;
__IO uint32_t RESERVED;
}NUMCOMP[DWT_NUMCOMP_VALUE];
}DWT_Type, *DWT_MemMapPtr;

In ARMv6m there is no cyccnt, cpicnt, exccnt, sleepcnt, sucnt, foldcnt module. But since there is a 6word hole from CTRL address to PCS, I kept the ones from CM4. 

According to ARM, there are n comp, mask and function modules, based on the value from CTRL. I could see that the CTRLval is 2 and not 4 like stated on the ref. manual. 

And ARM does not specify a 32bit "hole" from the end of functionto the start of compx+1. But I saw this on my debugger: 

pastedImage_8.png

looks like there is "something" 32 bit from NUMCOMP[0].function to NUMCOMP[1].comp, hence I added the RESERVED in the NUMCOMP structure to have NUMCOMP1 aligned. . 

Question1: Why there is an "hole" and what is there? Maybe I did not read correctly the ARMv6m architecture manual. 

Second point: from debugger I can see the content of DWT->CTRL, but in the code

volatile uint32_t numcomp = DWT->CTRL;

returns 0.

Furthermore, writings from the CPU to the DWT do not update the DWT content (in any register), while writing in the expression tab with the debugger updates and correctly triggers the watchpoint. 

Same issue with DEMCR register: writes from processor are ignored. 

Again, according to ARM, 

pastedImage_2.png

Question2: is it possible that on the S32K11x family the DWT is accessible only from the DAP and not from the processor?

Question3: if not question 2, which steps do I need to take to enable the DWT from the processor on S32K11x family MCUs?

According to ARM, CYCCNT is not present in armv6. But stepping from the debugger, I can see the value of CYCCNT increasing: 

pastedImage_13.png

pastedImage_14.png

etc.

I am not planning to use it in my application, but I am curious about it: 

Bonus Question4: What's in 0xe0001004 on the S32K11x MCUs?

Any hint would be gladly appreciated, 

K.R.

Luca.

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1 Solution
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danielmartynek
NXP TechSupport
NXP TechSupport

Hi Luca,

I'm sorry for the delayed response.

1.

According to the ARM®v6-M Architecture Reference Manual, there is an unspecified gap between DWT_Function0 and DWT_Comp1.

pastedImage_1.png
0xE0001020 DWT_COMP0
0xE0001024 DWT_MASK0
0xE0001028 DWT_FUNCTION0
0xE0001032
0xE0001036 DWT_COMP1
0xE000103A DWT_MASK1
0xE000103E DWT_FUNCTION1

2.

The core does not have access to DWT on S32K11x (Cortex M0+), unfortunately.

The current S32K1xx RM does not specify that, an update is under a discussion.

4.

I'm sorry, the address 0xe0001004 is not specified. 

Regards,

Daniel

.

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3 Replies
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danielmartynek
NXP TechSupport
NXP TechSupport

Hi Luca,

I'm sorry for the delayed response.

1.

According to the ARM®v6-M Architecture Reference Manual, there is an unspecified gap between DWT_Function0 and DWT_Comp1.

pastedImage_1.png
0xE0001020 DWT_COMP0
0xE0001024 DWT_MASK0
0xE0001028 DWT_FUNCTION0
0xE0001032
0xE0001036 DWT_COMP1
0xE000103A DWT_MASK1
0xE000103E DWT_FUNCTION1

2.

The core does not have access to DWT on S32K11x (Cortex M0+), unfortunately.

The current S32K1xx RM does not specify that, an update is under a discussion.

4.

I'm sorry, the address 0xe0001004 is not specified. 

Regards,

Daniel

.

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611 Views
Catosh
Contributor IV

Hello Daniel,

thanks for the clarification, no issues for the delay. 

One more point here: are there some implementation hints for the stack monitoring for the CM0+  that NXP can suggest or it's too much application dependent? For the underflow I suppose that placing the stack at the very top of the ram should be a good measure, what about overflow?

K.R.

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danielmartynek
NXP TechSupport
NXP TechSupport

Hello Luca,

There is no S32K11x-specific SW method for monitoring the stack.

But since the MCUs have MPU, the SRAM - core access can be restricted.

Regards,

Daniel