DMA to UART communication random behavior

[c_joshi]

Hi

I am trying to use DMA to send and recieve from UART. I configured the DMA successfully and also see the recieved data in the SRAM. But the recieved data is very inconsistent. Sometimes I recieve garbage value in the first four bytes and then the correct data. Sometimes I recieve at the correct location but data recieved is incorrect. Some other times I recieve correct data. What is the reason for this random behaviour?

I use the function " LPUART_DRV_ReceiveData"  which in turn uses LPUART_DRV_StartReceiveDataUsingDma and EDMA_DRV_ConfigMultiBlockTransfer. Should I make any changes in configMultiBlocktransfer function?

Or is this memory mapping issue?

I use blocking send and non-blocking recieve.

Also when I recieve correctly DMA stays in rxBusy state continuously. How can I make the DMA Rx channel get out of busy state?

Is using Blocking UART better? When I use blocking UART I dont recieve at all. Does this mean I am doing something wrong in configuration altogether? I know this is a lot of questions and very chaotic but thats how the functionality is behaving too.

Kindly help.

Thanks.

[danielmartynek]

Hi c.joshi@spike.global, 

Hard to say.

Could you attached a test project?

Thanks,

BR, Daniel

[c_joshi]

Hello Daniel, 

Thank you for your prompt response but due to some security reasons , I cannot attach the project. Fortunately I have been able to find some workaround. 

I am now clearing the destination buffer before receiving and i am getting the correct data. But I get the correct data after looping through the send and receive 2-3 times. 

I think the reason can be that the data is not available yet but DMA is transferring(junk data) anyway.

Now, How can I make DMA wait untill it receives the correct data from LPUART and then transfer it to destination buffer?

Thanks for your help.

Chandrika

[danielmartynek]

Hello Chandrika,

If the DMA trigger is the Receive Data Register Full Flag (RDRF), it triggers only of the data are received.
But the number of datawords available in the buffer when RDRF is set depends on the WATER[RXWATER] value.

Regards,
Daniel

[c_joshi]

Hi Daniel,

Could you please elaborate your answer? I have not changed anything wrt the RDRF or WATER[RXWATER]. Probably using the default values.  Can you tell me how it effects and what should I be changing in my code?

[danielmartynek]

Hi Chandrika,

I was reacting to this: "I think the reason can be that the data is not available yet but DMA is transferring(junk data) anyway."

Because the RDRF flag is a DMA trigger but it depends on the DMA configuration how many bytes is transferred on a single trigger. The RXWATER value specifies how many datawords are in the RX FIFO when the RDRF flag is set.

I believe it is explained in the RM.

I haven't seen the code, hard to say. 

BR, Daniel