DMA source address change issue

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DMA source address change issue

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aaronwang
NXP Employee
NXP Employee

Hi,

I meet a problem of DMA on S32K312 chip. The application scenario is moving the ADC sampling data to a fixed buffer by DMA.

The ADC1 channel data register address is set as the source address of DMA TCD1 channel, and the buffer address is set as the DMA destination address. But once the ADC sampling is triggered, the DMA source address changes (from 0x400A4118 to 0x400a117), and the CHE_ES register indicates the SAE and DAE errors.

The source address of DMA is configured as fixed address, and there is no place to change the SADDR register, it just changes actumatically.  Please see the attached pictures.

 

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Hi Aaron,

After checked the project and called, a preliminary conclusion is as follows:

  • The NBYTES field of DMA TCD1 channel is 0(incorrect value) and the DMA engine start with this value.

frank_yang_1_0-1729667153589.png

  • This resulted in SADDR and DADDR register unexpected behavior then cause the DMA error.  Details:
    • SADDR still decrements by 1 after a DMA minor loop (1 DMA request),although the SMLOE is disable.
    • DADDR add a significant offset(incorrect value) after a minor loop.
  • When setting NBYTES to the correct value, this issue will be solved. You could try it.

But there is a potential issue that the S32K3 RM don`t mentioned DMA behavior pattern like this. 

BR

Frank

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1,009件の閲覧回数

Hi Aaron,

After checked the project and called, a preliminary conclusion is as follows:

  • The NBYTES field of DMA TCD1 channel is 0(incorrect value) and the DMA engine start with this value.

frank_yang_1_0-1729667153589.png

  • This resulted in SADDR and DADDR register unexpected behavior then cause the DMA error.  Details:
    • SADDR still decrements by 1 after a DMA minor loop (1 DMA request),although the SMLOE is disable.
    • DADDR add a significant offset(incorrect value) after a minor loop.
  • When setting NBYTES to the correct value, this issue will be solved. You could try it.

But there is a potential issue that the S32K3 RM don`t mentioned DMA behavior pattern like this. 

BR

Frank

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aaronwang
NXP Employee
NXP Employee

Hi, Frank

Thank you so much. The issue has been fixed after trying your method. It's really weird the NBYTES setting can impact the SADDR register.

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