Critical inconsistency with S32K144 ADC_SC1x register between CPU specification and actual value

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Critical inconsistency with S32K144 ADC_SC1x register between CPU specification and actual value

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Contributor II

There is a critical inconsistency identified between ADC specification and actual register value for ADC_SC1x.

 

Actual value in S32DS:

ADCH field only has 5 bits available and setting 0x1F disables it.1.png

These are the register values in memory window:

 2.png

 

CPU specification:

ADCH field has 6 bits available and setting 0x3F disables it, while 0x1F is a reserved value.

3.png

4.jpg

5.jpg

Hope NXP can clarify this issue. Which one is correct?

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NXP TechSupport
NXP TechSupport

Hi,

the register description is general across S32K1xx family. Some of the input channel options might not be available for
S32K144.

pastedImage_2.png

BR, Petr