There is a critical inconsistency identified between ADC specification and actual register value for ADC_SC1x.
Actual value in S32DS:
ADCH field only has 5 bits available and setting 0x1F disables it.
These are the register values in memory window:
ADCH field has 6 bits available and setting 0x3F disables it, while 0x1F is a reserved value.
Hope NXP can clarify this issue. Which one is correct?
the register description is general across S32K1xx family. Some of the input channel options might not be available forS32K144.