Clarification about ECC in SRAM and Flash

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Clarification about ECC in SRAM and Flash

2,368 Views
Catosh
Contributor IV

Hi All, 

I am working on S32K11x platform. 

Some question related to safety manual assumptions about ECC (sram and flash):

Assumption: [SM_111] The ECC SRAM reporting has to be enabled by the software
application (in LMEM module), before the safety application starts. [end]

I suppose we are speaking of MCM_LMDRx here, since S321K11x do not have LMEM. 

In MCM_LMDRx for S32K11 the control field CF0 is reserved and read-only. The implication is that the ECC on SRAM_H is enabled by default in CM0 read and write family, and I can only enable or disable the interrupt generation in the error reporting module?

Then, in MCM_LMPECR I can see that ER1BR anc ERNCR:

This bit field is Reserved and Read-Only 0 for S32K11x variants. This bit field cannot mask ECC reporting, as a result the ECC would always be reported.

This is not clear for me. This refers to MCM_LMPEIR interrupts, because:

For S32K11x variants, MCM interrupt for ECC is not supported and this register only captures the event.

But then in ERM I can see that I can enable interrupts for ch0 for both correctable and non-correctable errors. Hence the reporting is enabled and notified in ERM module and not in MCM_LMEM for S32K11x mcu?

If the reporting is not activated, the correction of single correctable errors is still active? 

 

Then speaking about the Flash memory: 
It's not really clear for me the meaning of Assumption SM_119 in Safety manual rev.4: 

Assumption: [SM_119] The Flash memory ECC failure reporting path should be checked to validate if detected ECC faults are correctly reported. [end]

What's the meaning og the "Flash failure reporting path" since there is no EIM for the flash memory? 

Furthermore, this is a runtime check. Shall I perform this check once for FTTI or only before the activation of the mem controller or before reading data from flash?

Information about ECC flash events is provided in the FERSTAT of FTFC, is this part of the "failure reporting path"?

I'll be glad to have More information on this points.

[EDIT]: in FERCNFG the FDBFD field looks like it can be used as EIM exactly for this purpose. My fault in not reading it before in the RM.

K.R.

Luca. 

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4 Replies

1,808 Views
dianabatrlova
NXP TechSupport
NXP TechSupport

Hi Luca,

I would like to apologize for the delay.

The S32K11x devices do not have LMEM module but PRAMC instead.

The Cortex-M0+ doesn't have CODE bus, so the access to SRAM from CPU has to go through AXBS-Lite. 

Hence the reporting is enabled and notified in ERM module and not in MCM_LMEM for S32K11x mcu?

MCM interrupt for ECC is not supported and this register only ctaptures the event.

I have tried to test it and as we can see above the MCM register captures the event. So, we can see, for example, ECC fault address not only in ERM but also in MCM->LMFAR.

If the reporting is not activated, the correction of single correctable errors is still active?

If I disable ERM interrupt I can see that ERM still capture of address information on single-bit correction and non-correctable ECC events.

About Flash failure reporting path. The double-bit ECC error is indicated by FERSTAT[DFDIF] flag, more information can be seen in the section "36.5.2.5 ECC implementation for FlexNVM" 

 in FERCNFG the FDFD field looks like it can be used as EIM exactly for this purpose.

Yes, that is correct.

I hope it helps.

Best Regards,

Diana

1,808 Views
Catosh
Contributor IV

Hi Diana, 

one more question about Flash and ECC. 

In case of FERSTAT[DFDIF] are there registers that store the address that triggered the double bit access error, like in sram ERM? 

If so, where are this registers?

Thanks and best regards, 

Luca. 

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1,808 Views
dianabatrlova
NXP TechSupport
NXP TechSupport

Hi Luca,

On the S32K144 the address with double bit ECC error will cause to issue a BusFault exception after that the address can be found at BFAR register.

Unfortunately, this register is not available for the S32K118. However, there should be a possibility to debug the hards faults on the ARM Cortex-M0. I recommend you to look at a useful document created for the Kinetis devices

https://community.nxp.com/message/324125 

I hope it helps.

Best Regards,

Diana

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1,808 Views
Catosh
Contributor IV

Hi Diana, 

thanks for your support!

Another clarification is needed from my side: the PRAM controller is only related to the 128bytes of PRAM?

if I have a part number without cSEC the PRAM controller is still present on the MCU or will it assert an error if accessed, for example to write PRAM registers?

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