Can we use LPSPI with the module frequency 48MHz in Run Mode with FIRC?

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Can we use LPSPI with the module frequency 48MHz in Run Mode with FIRC?

Jump to solution
760 Views
Hozumi
Contributor I

Can we use LPSPI with the module frequency 48MHz in Run Mode with FIRC?

When using FIRC in Run Mode, the frequency of BUS CLK and LPSPI can be set to 48MHz.
Is this setting guaranteed to work?

S32K-RM.pdf Rev12.1 P.566 Table 27-8 has a description of "Maximum frequency governed by BUS_CLK", but in the data sheet Rev.11 Table 32. LPSPI electrical specifications, f_periph is Max. 40MHz in Run Mode.

Which description is correct?
If both are correct, why is f_periph limited to 40MHz in Run Mode?

0 Kudos
1 Solution
743 Views
Robin_Shen
NXP TechSupport
NXP TechSupport

Hi Ken3,

Please check the feedback from AE team:

I tested an SDK example “lpspi_transfer_s32k144” with S32K144-EVB, change the BUS_CLK to 48Mhz(If 40 MHz when using PLL as system clock source, S32K-RM, page 560), the LPSPI module is use FIRCDIV2_CLK which is 48Mhz, the program runs normally.

1.png2.png

 

But set BUS CLK to more 40Mhz maybe not an appropriate choice for the LPSPI slave or master communication except loopback according to the S32-DS’s LPSPI electrical specifications (page 52, Table 32), and I think 40Mhz is enough to achieve the max communication baud rate 10Mhz.

3.png

 

Also if the bus clock is same system clock, an asynchronous wakeup event during VLPS mode entry may result in possible system hang scenario according to ERR011063 in S32K142_0N33V Errata.

4.png

If the users use their code to perform VLPS mode transition must aware of this and take some measures. If use SDK’s pwrMan module, before actually doing the transition the program will switch to a temperate state with the SYS_CLK and BUS_CLK is set to the right value.

5.png

Best Regards,
Robin
-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

 

View solution in original post

0 Kudos
1 Reply
744 Views
Robin_Shen
NXP TechSupport
NXP TechSupport

Hi Ken3,

Please check the feedback from AE team:

I tested an SDK example “lpspi_transfer_s32k144” with S32K144-EVB, change the BUS_CLK to 48Mhz(If 40 MHz when using PLL as system clock source, S32K-RM, page 560), the LPSPI module is use FIRCDIV2_CLK which is 48Mhz, the program runs normally.

1.png2.png

 

But set BUS CLK to more 40Mhz maybe not an appropriate choice for the LPSPI slave or master communication except loopback according to the S32-DS’s LPSPI electrical specifications (page 52, Table 32), and I think 40Mhz is enough to achieve the max communication baud rate 10Mhz.

3.png

 

Also if the bus clock is same system clock, an asynchronous wakeup event during VLPS mode entry may result in possible system hang scenario according to ERR011063 in S32K142_0N33V Errata.

4.png

If the users use their code to perform VLPS mode transition must aware of this and take some measures. If use SDK’s pwrMan module, before actually doing the transition the program will switch to a temperate state with the SYS_CLK and BUS_CLK is set to the right value.

5.png

Best Regards,
Robin
-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

 

0 Kudos