Hi support Team,
I am using SD32K144 eval board.I wanted to use ADC0,ADC1 simultaneously in back to back to mode.I wanted to trigger ADC0 through PDB0 Channel0 and ADC1 through PDB0 Channel 1 in back to back mode.8 channel of ADC0 is working perfectly but Adc1 is not working kindly help me
Below is the code for PDB and ADC initialization.
void PDB_Init(void)
{
PCC->PCCn[PCC_PDB0_INDEX] |= PCC_PCCn_CGC_MASK; /* Enable bus clock in PDB0 */
PDB0->SC |= PDB_SC_TRGSEL(0xF) | /* b1111: Software trigger is selected */
PDB_SC_PRESCALER(1) | /* Prescaler: 010 = sysclck/(2*MULT) = 80 / (2*1) = 40MHz */
PDB_SC_MULT(0) | /* 00: Multiplication factor is 1. */
PDB_SC_PDBEN_MASK; /* 1: PDB enabled */
PDB0->CH[0].C1 |= PDB_C1_BB(0xFE) | /* DLY[0] : pre-trigger from PDB DLY */
/* DLY[7:1] : back-to-back enabled */
PDB_C1_TOS(0x00) | /* Pretrigger Output Select: 0=bypassed , 1=enabled */
PDB_C1_EN(0xff); /* PDB channel's [3:0] pre-trigger enabled */
PDB0->CH[1].C1 |= PDB_C1_BB(0x03) | /* DLY[0] : pre-trigger from PDB DLY */
/* DLY[3:1] : back-to-back enabled */
PDB_C1_TOS(0x00) | /* Pretrigger Output Select: 0=bypassed , 1=enabled */
PDB_C1_EN(0x03); /* PDB channel's [3:0] pre-trigger enabled */
// PDB0->MOD = 2200;
// PDB0->IDLY = 2200;
// PDB0->CH[0].DLY[0] = 100; /* Pretrigger 0 : 100 * 25e-9 = 2.5e-6 */
PDB0->SC |= PDB_SC_LDOK_MASK;
}
void ADC_Init(void)
{
/* ADC0 configuration */
PCC->PCCn[PCC_ADC0_INDEX] &= ~PCC_PCCn_CGC_MASK; /* Disable clock to change PCS */
PCC->PCCn[PCC_ADC0_INDEX] |= PCC_PCCn_PCS(6); /* PCS=3: Select SPLL */
PCC->PCCn[PCC_ADC0_INDEX] |= PCC_PCCn_CGC_MASK; /* Enable bus clock in ADC */
ADC0->CFG1 |= ADC_CFG1_ADICLK(0) | /* Only ALTCLK1 is available */
ADC_CFG1_ADIV(2) | /* the clock rate is (input clock)/4 */
ADC_CFG1_MODE(1); /* 0b00: 8-bit, 0b01: 12-bit, 0b10: 10-bit */
ADC0->SC2 |= ADC_SC2_ADTRG(1); /* Conversion Trigger: 0b0= SW , 0b1 = HW */
ADC0->SC3 |= ADC_SC3_AVGE(1)|ADC_SC3_AVGS(3);
ADC0->SC1[0] = ADC_SC1_ADCH(12); /* Select AD12 (ADC0_SE12) @PTC14 */
ADC0->SC1[1] = ADC_SC1_ADCH(13); /* Select AD12 (ADC0_SE12) @PTC14 */
ADC0->SC1[2] = ADC_SC1_ADCH(0); /* Select AD12 (ADC0_SE12) @PTC14 */
ADC0->SC1[3] = ADC_SC1_ADCH(6); /* Select AD12 (ADC0_SE12) @PTC14 */
ADC0->SC1[4] = ADC_SC1_ADCH(8); /* Select AD12 (ADC0_SE12) @PTC14 */
ADC0->SC1[5] = ADC_SC1_ADCH(9); /* Select AD12 (ADC0_SE12) @PTC14 */
ADC0->SC1[6] = ADC_SC1_ADCH(2); /* Select AD12 (ADC0_SE12) @PTC14 */
ADC0->SC1[7] = ADC_SC1_ADCH(5); /* Select AD12 (ADC0_SE12) @PTC14 */
PCC->PCCn[PCC_ADC1_INDEX] &= ~PCC_PCCn_CGC_MASK; /* Disable clock to change PCS */
PCC->PCCn[PCC_ADC1_INDEX] |= PCC_PCCn_PCS(6); /* PCS=3: Select SPLL */
PCC->PCCn[PCC_ADC1_INDEX] |= PCC_PCCn_CGC_MASK; /* Enable bus clock in ADC */
/* ADC1 configuration */
ADC1->CFG1 |= ADC_CFG1_ADICLK(0) | /* Only ALTCLK1 is available */
ADC_CFG1_ADIV(2) | /* the clock rate is (input clock)/4 */
ADC_CFG1_MODE(1); /* 0b00: 8-bit, 0b01: 12-bit, 0b10: 10-bit */
ADC1->SC2 |= ADC_SC2_ADTRG(1); /* Conversion Trigger: 0b0= SW , 0b1 = HW */
ADC1->SC3 |= ADC_SC3_AVGE(1)|ADC_SC3_AVGS(3);
ADC1->SC1[0] = ADC_SC1_ADCH(10); /* Select AD12 (ADC1_SE10) @PTC14 */
ADC1->SC1[0] = ADC_SC1_ADCH(2); /* Select AD12 (ADC0_SE2) @PTC14 */
}
Thanks
Nitin verma
