Can an incorrect implementation of SRAM retention permanently damage a uP?

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Can an incorrect implementation of SRAM retention permanently damage a uP?

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toddsteinmetz
Contributor I
I was using the S32K144 Dev Kit and I was starting to explore the SRAM retention feature I intend to use through a software reset to return to a bootloader. I wrote 0 to SRAMU_RETEN and SRAML_RETEN stopping at a breakpoint immediately after to inspect the registers and then not following the directions I allowed the software to continue normally where accesses to RAM were attempted. It seems this experiment bricked my Dev Kit. Immediately after this experiment, I can no longer connect to it with the debugger and can no longer JTAG program it, whereas a second Dev Kit in my office remains fully functional with my tools. Is this some coincidence with a different failure on my Dev Kit or is it actually possible to destroy a uP by misuse of the SRAM retention feature? My expectation was that a hardware power cycle would clear out any mis-use of this feature, but perhaps this was an incorrect assumption? As reference I am reading 31.3.4 of S32KReferenceManual, Rev 7, 04/2018 which clearly states 'ensure that no accesses occur to RAM with retained contents' but the manual does not go on to tell what may be the consequences if software is written that disobeys this statement. Thanks, Todd.
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danielmartynek
NXP TechSupport
NXP TechSupport
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danielmartynek
NXP TechSupport
NXP TechSupport
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toddsteinmetz
Contributor I

Daniel,

This has fully recovered my dev kit !

You and Oliver Tian are amazing !

Thank You !

Todd.

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