CMU clock failure recovery mechanisms

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CMU clock failure recovery mechanisms

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Pusoy
Contributor III

Hi,

In the Clocking section of the reference manual, there is a description regarding the failure handling mechanism of FIRC. However, according to Table 157 in the manual, CMU_FC_4 and CMU_FC_5 are not referenced to FXOSC_CLK.

  1. How should we interpret the highlighted portion in the first diagram?

Pusoy_2-1703820358503.png

 

Pusoy_1-1703820308283.png

As shown in the third diagram, when FIRC_CLK is used as the source for the system clock (CORE_CLK), AIPS_PLAT_CLK and HSE_CLK also derive from FIRC_CLK. The reference clocks for CMU_FC_4 and CMU_FC_5 are also FIRC_CLK.

2. So, if there are errors with AIPS_PLAT_CLK and HSE_CLK, does it mean that CMU_FC_4 and CMU_FC_5 cannot detect those errors?

Pusoy_3-1703820770648.png

 

 

 

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danielmartynek
NXP TechSupport
NXP TechSupport

Hello @Pusoy,

The CMU_FC_4 / 5 both use the FIRC as the reference clock.

Section 24.4.4.1 is incorrect and will be updated.

 

Regards,

Daniel

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