Hi
I am currently designing the CAN FD configurations, and i have some doubts i like to share with you :
1)My PE clock is 40MHz. is it the CANCLK or Sclock ?
2) Prescaler division factor , is it before added (+ 1) or after?
3) if I want to configure bit timing for the nominal phase when the following are enabled for CAN FD.
according to the RM i should follow the image below, right ?
4) when configuring , which value do i need to put , do i need to put the value for PSEG1 , FPSEG2 etc or the value of Time segments 1 and 2 ? Time quanta is it = Time segment 1 + Time segment 2 ?
Hi @Ayaz,
1) PE Clock refers to CANCLK.
2) Before Tq.
3) & 4) Please refer to
for bit timing calculation.
Best regards,
Julián