After disabling the PLL, SPLLVLD-Bit is not set to 0 (S32K144)

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After disabling the PLL, SPLLVLD-Bit is not set to 0 (S32K144)

240 Views
adrianvoswincke
Contributor I

Hello,

before I go into MCU VLP mode, I configure the clock distribution. For this I set the slow IRC as a system clock, then switch off the fast IRC and the system oscilator clock and finally I switch off the PLL. To turn off the PLL, I check that it is not being used as a system clock, then set the SPLLEN bit to zero and wait until the SPLLVLD bit becomes zero. In some MCUs tested, the SPLLVLD bit is never set to zero. In the explanation of the SPLLVLD bit in the Reference Manual, I found the comment that this should only be used for checking after the PLL has been initialized. My question would be how do I check if the PLL is switched off after setting SPLLEN bit to zero?

    /*
     * SCG->SPLLCSR:
     * [25] SPLL = 0x0 SPLL is not the system clock source
     */
    if((SCG->SPLLCSR & SCG_SPLLCSR_SPLLSEL_MASK) != SCG_SPLLCSR_SPLLSEL_MASK)
    {
        /*
         * SCG->SPLLCSR:
         * [0] SPLLEN = 0 SPLL disabled
         */
        SCG->SPLLCSR &= ~SCG_SPLLCSR_SPLLEN_MASK;

        /*
         * SCG->SPLLCSR:
         * [24] SPLLVLD = 0 SPLL is not enabled or clock is not valid
         */
        while((SCG->SPLLCSR  & SCG_SPLLCSR_SPLLVLD_MASK) == SCG_SPLLCSR_SPLLVLD_MASK) { }
    }

Greetings

Adrian Voswinckel

2 Replies

188 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hello Adrian,

You can read the SPLLEN bit back.

However, the issue here is that the SPLL is using SOSC as a source clock.

Could you please disable SPLL first and then SOSC and FIRC?

Thank you,

Regards,

Daniel

0 Kudos

188 Views
adrianvoswincke
Contributor I

Hello Daniel,

thank you for your fast response. After changing the order of the clock switch-off, the error no longer occurred.

Regards

Adrian