AN12218SW Bootloader doesn't properly reset SCG->FIRCDIV and PCC->LPUART prior to app jump.

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AN12218SW Bootloader doesn't properly reset SCG->FIRCDIV and PCC->LPUART prior to app jump.

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lucianomoretti
Contributor IV

While debugging peripheral clocking issues after jumping from the bootloader I found the following in the clocks.c reset_clock() function:

SCG->FIRCDIV |= SCG_FIRCDIV_FIRCDIV2(0b000); /* Disable FIRC divider */


This code does not change the FIRDIV register because it is an "or" with zeros.

The corrected code is:

SCG->FIRCDIV &= ~SCG_FIRCDIV_FIRCDIV2(0b111); /* Disable FIRC divider */

 

The code also does not restore the clock source for the LPUARTs in the Uart.c void UART_Reset(LPUART_Type *pUART) function to the original clock source of '0', leaving it set to clock source 3 as set in the UART_Init function.

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lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi,

thank you for bringing this into our attention, I will report it. The application note should be updated in the near future.

Regards,

Lukas

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lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi,

thank you for bringing this into our attention, I will report it. The application note should be updated in the near future.

Regards,

Lukas

View solution in original post

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