ADC0 multichannel uses DMA handling

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ADC0 multichannel uses DMA handling

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linglei_meng
Contributor II
S32K148 -> 144 LQFP
 
Hi community,
 
1. How to configure the ADC0 multi-channel to use a DMA for handling.
 
2. DMA transfers multiple ADC data at the same time, how to distinguish which ADC0_SE2 data?Which is ADC_SE6 data?
 
 
 
ADC0_SE2
ADC0_SE6
ADC0_SE19
ADC0_SE7
ADC0_SE8
ADC0_SE9
ADC0_SE12
ADC0_SE13
ADC0_SE14
ADC0_SE15
ADC0_SE26
ADC0_SE27
ADC0_SE28
ADC0_SE30
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Robin_Shen
NXP TechSupport
NXP TechSupport

Hi linglei_meng,

Seems that you are refer: Example S32K144 PDB ADC DMA 32DS.ARM.2018.R1.

And assume you have configure:
ADC0_SE2 as channel of adConv0_ChnConfig0
ADC0_SE6 as channel of adConv0_ChnConfig1
Then ADC0_SE2 should be the 1th element of buffer, and the ADC0_SE6 should be the 2th element of buffer.

S32K144_PDB_ADC_DMA_sdk_rtm_300.png

You can configure Input Channel of adConv0_ChnConfig0 in adConv0, and the generated codes can be found in adConv0.c.

configure ADC Input Channel.png

Best Regards,
Robin
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Robin_Shen
NXP TechSupport
NXP TechSupport

Hi linglei_meng,

Seems that you are refer: Example S32K144 PDB ADC DMA 32DS.ARM.2018.R1.

And assume you have configure:
ADC0_SE2 as channel of adConv0_ChnConfig0
ADC0_SE6 as channel of adConv0_ChnConfig1
Then ADC0_SE2 should be the 1th element of buffer, and the ADC0_SE6 should be the 2th element of buffer.

S32K144_PDB_ADC_DMA_sdk_rtm_300.png

You can configure Input Channel of adConv0_ChnConfig0 in adConv0, and the generated codes can be found in adConv0.c.

configure ADC Input Channel.png

Best Regards,
Robin
-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
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linglei_meng
Contributor II
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linglei_meng
Contributor II

I looked at its example(Hard to trigger).

No DMA triggered.

Attached is my project.

 

void ADC_Init(void)
{
ADC1_Init();

PDB1_init();

DMA_Init();
#if 1
// Initialize TRGMUX to route LPIT0 ch0 trigger to both PDBs and PDB's OUT pulse to TRGMUX out7
TRGMUX_DRV_Init(INST_TRGMUX1, &trgmux1_InitConfig0);

// Initialize LPIT instance 0. Reset and enable peripheral
LPIT_DRV_Init(INST_LPIT1, &lpit1_InitConfig);
// Initialize LPIT channel 0 to generate trigger for PDB via TRGMUX
LPIT_DRV_InitChannel(INST_LPIT1, 0, &lpit1_ChnConfig0);
// Start LPIT0 channel 0 counter
LPIT_DRV_StartTimerChannels(INST_LPIT1, 1);
#endif
}

 

static void ADC1_Init(void)
{
ADC_DRV_AutoCalibration(INST_ADCONV1);
ADC_DRV_ConfigConverter(INST_ADCONV1, &adConv1_ConvConfig0);

ADC_DRV_ConfigChan(INST_ADCONV1, 0UL, &adConv1_ChnConfig0);
ADC_DRV_ConfigChan(INST_ADCONV1, 1UL, &adConv1_ChnConfig1);
ADC_DRV_ConfigChan(INST_ADCONV1, 2UL, &adConv1_ChnConfig2);
ADC_DRV_ConfigChan(INST_ADCONV1, 3UL, &adConv1_ChnConfig3);
ADC_DRV_ConfigChan(INST_ADCONV1, 4UL, &adConv1_ChnConfig4);
}

 

static void PDB1_init(void)
{
PDB_DRV_Init(INST_PDB1, &pdb1_InitConfig0);
PDB_DRV_Enable(INST_PDB1);

// config 8 pretriggers on ch0 based on component setting
PDB_DRV_ConfigAdcPreTrigger(INST_PDB1, 0UL , &pdb1_AdcTrigInitConfig0);
PDB_DRV_ConfigAdcPreTrigger(INST_PDB1, 0UL , &pdb1_AdcTrigInitConfig1);
PDB_DRV_ConfigAdcPreTrigger(INST_PDB1, 0UL , &pdb1_AdcTrigInitConfig2);
PDB_DRV_ConfigAdcPreTrigger(INST_PDB1, 0UL , &pdb1_AdcTrigInitConfig3);
PDB_DRV_ConfigAdcPreTrigger(INST_PDB1, 0UL , &pdb1_AdcTrigInitConfig4);

// config 1 pretrigger on ch1 based on component setting
PDB_DRV_ConfigAdcPreTrigger(INST_PDB1, 1UL , &pdb1_AdcTrigInitConfig0);

// set PDB1 counter period to delayValue (~30us)
PDB_DRV_SetTimerModulusValue(INST_PDB1,(uint32_t) delayValue);
// set ch0 trigger delay to happen immediate upon Trigger_In 0 (PIT0 ch0)
PDB_DRV_SetAdcPreTriggerDelayValue(INST_PDB1, 0UL , 0UL , (uint32_t) (1));
// set ch1 trigger0 delay to happen 10us upon Trigger_In 0 (PIT0 ch0)
PDB_DRV_SetAdcPreTriggerDelayValue(INST_PDB1, 1UL , 0UL , (uint32_t) (10*delayValue/PDLY_TIMEOUT));

PDB_DRV_LoadValuesCmd(INST_PDB1);
}

/* This function triggers a loop memory-to-memory transfer. */
static void triggerLoopTransfer(uint8_t channel, uint8_t * srcBuff, uint16_t * dstBuff, uint32_t size)
{
//transferComplete = false;

dma_request_source_t DmaReq;

/* configure transfer source and destination addresses */
transferConfig.srcAddr = (uint32_t)srcBuff;
transferConfig.destAddr = (uint32_t)dstBuff;
transferConfig.srcLastAddrAdjust = -(4*size);
transferConfig.destLastAddrAdjust = -(2*size);
loopConfig.majorLoopIterationCount = size;

if(channel == 0)
{
DmaReq = EDMA_REQ_ADC0;
}
else
{
DmaReq = EDMA_REQ_ADC1;
}

/* configure the eDMA channel for a loop transfer (via transfer configuration structure */
EDMA_DRV_ConfigLoopTransfer(channel, &transferConfig);

/* select hw request */
EDMA_DRV_SetChannelRequestAndTrigger(channel, DmaReq, false);

/* start the channel */
EDMA_DRV_StartChannel(channel);
}

static void DMA_Init(void)
{
EDMA_DRV_Init(&dmaController1_State, &dmaController1_InitConfig0, edmaChnStateArray, edmaChnConfigArray, EDMA_CONFIGURED_CHANNELS_COUNT);

// set DMA ch0 to read first 16 ADC0 Results registers and move it to buffer array starting from 1st element
triggerLoopTransfer(DMA_CHANNEL0, (uint8_t *)&(ADC0->R[0]),buffer, 16);
// set DMA ch1 to read first 9 ADC1 Results registers and move it to buffer array starting from 16th element
triggerLoopTransfer(DMA_CHANNEL1, (uint8_t *)&(ADC1->R[0]),&buffer[16], 9);
}

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Robin_Shen
NXP TechSupport
NXP TechSupport

Let us discuss this in your post: ADC PDB DMA (Hardware trigger)

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