ADC sampling time per ADC channel

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ADC sampling time per ADC channel

1,109 Views
Moises
Contributor I

Hello Nxp,

On my project we have different ADC channels (same group) on ADC0. Each of those has a different external circuit (Source impedance, Filter resistance...)

According reference manual:

"ADC TOTAL CONVERSION TIME = Sample Phase Time (set by SMPLTS + 1) + Hold
Phase (1 ADC Cycle) + Compare Phase Time (8-bit Mode = 20 ADC Cycles, 10-bit
Mode = 24 ADC Cycles, 12-bit Mode = 28 ADC Cycles) + Single or First continuous
time adder (5 ADC cycles + 5 bus clock cycles)"

My question is: is it possible to set individual sampling times per ADC channel? (maybe with channel delays in PDB pretriggers)

 

Thanks in advance

Moises

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uC: S32K188

EB Tresos 24.0.1

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3 Replies

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davidtosenovjan
NXP TechSupport
NXP TechSupport

Hi, sample time setting is given by CFG2[SMPLTS] and it is group setting. Possible trigger delays does not lengthen sampling time anyhow. So the answer is no, it cannot be configured per channel.

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Moises
Contributor I

Thanks for the fast reply;

>>sample time setting is given by CFG2[SMPLTS] and it is group setting. 

could be done by creating different groups?

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davidtosenovjan
NXP TechSupport
NXP TechSupport

I am sorry, I haven't meant group in this meaning. I just meant all channels.

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