ADC dataregisters on S32K3 vs S32K1

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ADC dataregisters on S32K3 vs S32K1

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FelixR
Contributor II

Hello there People,

the S32K1 had the feature that one ADC unit had data registers from RA, RB acending to RAF.

Those Dataregisters were independen from the physical pins. So I could have a mapping like this:

ADC ChannelPinData Register
ADCAS9RA
ADCBS2RB
ADCCS15RC

This did ensure that the data would always be in a acending order inside a known memory location so the DMA Unit had an easy time moving data.

However I don't find any similar functionality on the S32K3. Data is always scatterd between the PCDRn ICDR0n and ECDRn. So I can't just set the DMA unit to pick samples from one acending location for a defined range.

Yes I could use the BCTU to collect all ADC samples inside the BCTU adc data register and have a constant DMA source adress but this limits the possible ADC channels to 16 configurable channels. Right now I need 36 ADC Channels acros all ADC Units on the S32K324

Is there a function on the S32K3 which organizes the ADC Data maybe in something like a shadowregister or an adress from where I can transfer it easily?

Edit: Yes using acending ADC Channels would be an option. But this is highly unlikely to happen in praxis because of multiplexed pin functions with other periphery.

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

no such functionality is available in S32K3 ADC module. You are correct with available options, just BCTU allows up to 32 ADC channels to be converted using channel list.

BR, Petr

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

no such functionality is available in S32K3 ADC module. You are correct with available options, just BCTU allows up to 32 ADC channels to be converted using channel list.

BR, Petr

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FelixR
Contributor II

Hey @PetrS,

thanks for the response. That is quite unfortunate. However I did stumble uppon the scatter/gather feature of the eDMA unit. This should be what I am looking for.

With this I did setup a TCL for each ADC channel which I use with their data register as Source and a acending memory location at the destination. Now I experience that the eDMA unit cycles through the configured TCL sets and the source and destination adress match with my expectations. However Data is not moved.

If I don't use the scatter/gather feature Data is moved to the defined locations. Do I have to set anything else than the ESG Bit inside the TCDn_CSR Register?

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

not sure here, should be fine to know how DMA is enabled in ADC and what is DMA TDC config at all.
But if you see DMA is cycling between configured descriptors, then transfer should be executed. How is your configuration when SGA is not used and data is transferred properly?
Should not be better to enable DMA for last converted channel in chain and then read all data registers into buffer and then picked just data you needed from this array? Sur if this is suitable in your application.

BR, Petr

 

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