I am working on S32G3 (Yocto BSP 43) and trying to log secure-boot (BL2) errors into QSPI NOR.
I tried to use the MMIO read/write APIs from BL2; however, the boot process appears to halt immediately after the API call.
I attempted to use xspi_read() / xspi_write() APIs, but BL2 build fails with undefined reference errors. On inspection, these APIs are not implemented in ATF; same with FSPI read/write APIs
Could you please confirm whether read/write access from BL2 is supported when secure boot is enabled? If it is supported, could you advise which APIs are recommended for this use case? Alternatively, I would appreciate your guidance on feasible approaches or recommended alternatives for logging or data persistence from BL2.
Best regards,
Jayashree
Thank you for the quick response. As per your suggestion, I have included the recommended header file and attempted to call the XSPI APIs in the bl2_main.c file. However, I am still encountering an undefined reference/ symbol error during the build.
For your reference, I have attached the modified file below. I would appreciate it if you could please review it and let me know if I am missing any required configuration or build changes.
/*
* Copyright (c) 2013-2023, Arm Limited and Contributors.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <stdint.h>
#include <arch_helpers.h>
#include <arch_features.h>
#include <bl1/bl1.h>
#include <bl2/bl2.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <drivers/auth/auth_mod.h>
#include <drivers/auth/crypto_mod.h>
#include <drivers/console.h>
#include <drivers/fwu/fwu.h>
#include <drivers/nxp/flexspi/fspi_api.h>
#include <lib/bootmarker_capture.h>
#include <lib/extensions/pauth.h>
#include <lib/pmf/pmf.h>
#include <plat/common/platform.h>
#include "bl2_private.h"
#ifdef __aarch64__
#define NEXT_IMAGE "BL31"
#else
#define NEXT_IMAGE "BL32"
#endif
/* ================= NOR TEST CONFIG ================= */
#define NOR_TEST_OFFSET 0x400U
#define NOR_TEST_SIZE 4U
/* ================================================== */
#if ENABLE_RUNTIME_INSTRUMENTATION
PMF_REGISTER_SERVICE(bl_svc, PMF_RT_INSTR_SVC_ID,
BL_TOTAL_IDS, PMF_DUMP_ENABLE);
#endif
#if RESET_TO_BL2
/*******************************************************************************
* Setup function for BL2 when RESET_TO_BL2=1
******************************************************************************/
void bl2_el3_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
u_register_t arg3)
{
/* Perform early platform-specific setup */
bl2_el3_early_platform_setup(arg0, arg1, arg2, arg3);
/* Perform late platform-specific setup */
bl2_el3_plat_arch_setup();
#if CTX_INCLUDE_PAUTH_REGS
/*
* Assert that the ARMv8.3-PAuth registers are present or an access
* fault will be triggered when they are being saved or restored.
*/
assert(is_armv8_3_pauth_present());
#endif /* CTX_INCLUDE_PAUTH_REGS */
}
#else /* RESET_TO_BL2 */
/*******************************************************************************
* Setup function for BL2 when RESET_TO_BL2=0
******************************************************************************/
void bl2_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
u_register_t arg3)
{
/* Perform early platform-specific setup */
bl2_early_platform_setup2(arg0, arg1, arg2, arg3);
/* Perform late platform-specific setup */
bl2_plat_arch_setup();
#if CTX_INCLUDE_PAUTH_REGS
/*
* Assert that the ARMv8.3-PAuth registers are present or an access
* fault will be triggered when they are being saved or restored.
*/
assert(is_armv8_3_pauth_present());
#endif /* CTX_INCLUDE_PAUTH_REGS */
}
#endif /* RESET_TO_BL2 */
/*******************************************************************************
* The only thing to do in BL2 is to load further images and pass control to
* next BL. The memory occupied by BL2 will be reclaimed by BL3x stages. BL2
* runs entirely in S-EL1.
******************************************************************************/
void bl2_main(void)
{
entry_point_info_t *next_bl_ep_info;
uint32_t write_val = 0xA5A5A5A5;
uint32_t read_val = 0;
int rc;
#if ENABLE_RUNTIME_INSTRUMENTATION
PMF_CAPTURE_TIMESTAMP(bl_svc, BL2_ENTRY, PMF_CACHE_MAINT);
#endif
NOTICE("BL2: %s\n", version_string);
NOTICE("BL2: %s\n", build_message);
/* Perform remaining generic architectural setup in S-EL1 */
bl2_arch_setup();
#if PSA_FWU_SUPPORT
fwu_init();
#endif /* PSA_FWU_SUPPORT */
crypto_mod_init();
/* Initialize authentication module */
auth_mod_init();
/* Initialize the Measured Boot backend */
bl2_plat_mboot_init();
/* Initialize boot source */
bl2_plat_preload_setup();
/* ============================================================
* XSPI / NOR DIRECT ACCESS TEST (PERSISTENT LOGGING EXPERIMENT)
* ============================================================ */
NOTICE("\n===============================================\n");
NOTICE("BL2: XSPI NOR direct access test\n");
NOTICE("BL2: NOR offset = 0x%x\n", NOR_TEST_OFFSET);
NOTICE("===============================================\n");
NOTICE("BL2: Writing 0x%08x to NOR\n", write_val);
rc = xspi_write(NOR_TEST_OFFSET, &write_val, sizeof(write_val));
if (rc != 0) {
ERROR("BL2: xspi_write FAILED (%d)\n", rc);
} else {
NOTICE("BL2: xspi_write OK\n");
}
NOTICE("BL2: Reading back from NOR\n");
rc = xspi_read(NOR_TEST_OFFSET, &read_val, sizeof(read_val));
if (rc != 0) {
ERROR("BL2: xspi_read FAILED (%d)\n", rc);
} else {
NOTICE("BL2: xspi_read OK, value = 0x%08x\n", read_val);
}
NOTICE("===============================================\n");
NOTICE("BL2: XSPI NOR test done, continuing boot\n");
NOTICE("===============================================\n\n");
/* Load the subsequent bootloader images. */
next_bl_ep_info = bl2_load_images();
/* Teardown the Measured Boot backend */
bl2_plat_mboot_finish();
#if !BL2_RUNS_AT_EL3
#ifndef __aarch64__
/*
* For AArch32 state BL1 and BL2 share the MMU setup.
* Given that BL2 does not map BL1 regions, MMU needs
* to be disabled in order to go back to BL1.
*/
disable_mmu_icache_secure();
#endif /* !__aarch64__ */
#if ENABLE_PAUTH
/*
* Disable pointer authentication before running next boot image
*/
pauth_disable_el1();
#endif /* ENABLE_PAUTH */
#if ENABLE_RUNTIME_INSTRUMENTATION
PMF_CAPTURE_TIMESTAMP(bl_svc, BL2_EXIT, PMF_CACHE_MAINT);
#endif
console_flush();
/*
* Run next BL image via an SMC to BL1. Information on how to pass
* control to the BL32 (if present) and BL33 software images will
* be passed to next BL image as an argument.
*/
smc(BL1_SMC_RUN_IMAGE, (unsigned long)next_bl_ep_info, 0, 0, 0, 0, 0, 0);
#else /* if BL2_RUNS_AT_EL3 */
NOTICE("BL2: Booting " NEXT_IMAGE "\n");
print_entry_point_info(next_bl_ep_info);
#if ENABLE_RUNTIME_INSTRUMENTATION
PMF_CAPTURE_TIMESTAMP(bl_svc, BL2_EXIT, PMF_CACHE_MAINT);
#endif
console_flush();
#if ENABLE_PAUTH
/*
* Disable pointer authentication before running next boot image
*/
pauth_disable_el3();
#endif /* ENABLE_PAUTH */
bl2_run_next_image(next_bl_ep_info);
#endif /* BL2_RUNS_AT_EL3 */
}
