"Synchronous Abort" handler, esr 0x96000006

[Quentin2022]

Hi：

I encountered the following problem：

Warning: eth_eqos (eth0) using random MAC address - ee:29:c8:4a:05:1c
eth0: eth_eqosFailed to set the frequency of mac2_rx_rgmii
Failed to enable mac2_rx_rgmii clock
PFE: emac0: sgmii emac1: sgmii emac2: rgmii
"Synchronous Abort" handler, esr 0x96000006
elr: 00000000ffade6bc lr : 00000000ffadfc78 (reloc)
elr: 00000000ffade6bc lr : 00000000ffadfc78
x0 : 0000000000000000 x1 : 0000000000000000
x2 : 0000000000000000 x3 : 00000000200014b0
x4 : 000000008c7414b0 x5 : 0000000020000c74
x6 : 000000000000083e x7 : 0000000000000002
x8 : 0000000000000007 x9 : 0000000000000004
x10: 0000000000000000 x11: 00000000200014b2
x12: 0000000000000008 x13: 0000000000000000
x14: 00000000ffa99000 x15: 0000000000000021
x16: 00000000ffacd560 x17: 0000000000000000
x18: 00000000ffa01e70 x19: 00000000ffb36138
x20: 00000000ffe354ac x21: 0000000000000000
x22: 0000000000000008 x23: 00000000ffe0d034
x24: 0000000000000011 x25: 00000000ffb10ad9
x26: 00000000ffb10bd0 x27: 00000000ffb10b91
x28: 00000000ffe0d000 x29: 00000000ffde6de0

Code: 9400733a 17ffffef 128007a0 17fffff1 (b9400001)
Resetting CPU ...

I checked the code and found that it was because I disabled qspi in uboot.but I don't understand why this is happening. My startup method is emmc.

So can you help me clarify the reason or tell me how to debug this problem.

verythanks

[MayanksPatel]

Hi @Quentin2022,

Thanks for informing us.

Can we close this ticket if the issue got resolved?

[Quentin2022]

Yes.very thanks for you

[MayanksPatel]

Hi @Quentin2022,

Thank you for reaching out to us.

Please share the u-boot version which you used and the changes you did to disable the qspi.

I am trying to create the setup same as you.

Thanks,

Mayank s Patel

[Quentin2022]

Hi：

my uboot version is bsp32

The code changes are as follows:

--- a/u-boot/arch/arm/dts/fsl-s32gxxxardb.dtsi
+++ b/u-boot/arch/arm/dts/fsl-s32gxxxardb.dtsi

@@ -294,6 +294,7 @@
&qspi {
pinctrl-0 = <&pinctrl0_qspi>;
pinctrl-names = "default";
+ status = "disabled";
};

--- a/u-boot/arch/arm/dts/fsl-s32g.dtsi
+++ b/u-boot/arch/arm/dts/fsl-s32g.dtsi
@@ -204,7 +204,7 @@
};

&qspi {
- status = "okay";
+ status = "disabled";

mx25uw51245g@0 {
#address-cells = <1>;

The steps to reproduce are as follows:

1.change code and build 

2.use s32ft flash fip to emmc

3.power on,boot with EMMC  and enter uboot,use tftp and nfs  enter  kernel,then falsh kernel and rootfs in emmc

4.Starting again will cause this problem

[MayanksPatel]

Hi @Quentin2022,

Thanks for sharing the information.

1. Which board you are using? S32G274aevb or S32G274aRDB2?

2. Have you set the switches for booting from the emmc? Please share switch values here.

Thanks,

Mayank s Patel

[Quentin2022]

Hi:

Which board you are using?

------>s32g399ardb3

Have you set the switches for booting from the emmc?

-------yes.BOOT_RCON_B6 B7,value:11

[Quentin2022]

Hi，

I have resolved this issue and found that it seems to be caused by a clock conflict with PFE. I closed PFE in uboot and the problem was resolved.