in S32G2, DRAM reserved method to prevent DRAM initialisation from soft-reset

[starface42]

Hello,

I am inquiring about the DRAM reserved area for the S32G2.

I plan to use ramoops to store DRAM data on the eMMC.

However, the DRAM data gets reset when the device reboots due to a reset, causing the data to be lost. To address this issue, I added reserved-memory to the FDT to preserve the DRAM data across resets. Despite this, the DRAM values still get reset upon rebooting.

I would appreciate any suggestions or solutions you might have for this problem.

I am wondering if adding `mmap_region_t` in `plat/nxp/s32/s32_bl2_el3.c` would allow for the preservation of the DRAM area.

I have added a new area, but setting only the MT_RW attribute did not enable writing.

Furthermore, the values written by the kernel are still being erased due to DRAM initialization after a soft-reset.

Could you advise on how to correctly configure the DRAM area to prevent data loss after a soft-reset? Specifically, are there additional attributes or configurations required beyond MT_RW to ensure the DRAM area is both writable and persistent across warm-resets(soft reset)?

[Daniel-Aguirre]

Hi,

On regards of DRAM retention, the following information is provided under the S32G2 RM [Page 1566, S32G2 Reference Manual, Rev. 7, February 2023]:

Don't know if it helps.

Please, let us know.

[starface42]

Hello,

Thank you for your response.

I understand that retention is about maintaining DRAM data even when the power is off.

Is there a way to prevent certain areas of DRAM data from being cleared when the SoC is simply reset

(either from a reset in U-boot or a reboot command in the kernel)?

Thanks!

[Daniel-Aguirre · Accepted solution]

Hi,

Thanks for your feedback. The following is told under the S32G2 RM:

For which, the steps provided before, should enable the retention either under the standby power state or a functional reset.

As for specific areas, we are not seeing anything on this regard. We understand that all the DRAM values are being retained under this mode.

Please, let us know.

[starface42]

Sorry for getting back to you late. I’ve taken a look at what you suggested, and it seems like it doesn’t quite fit with what we need.

We’re planning to go with having the M7 core reset the A53 core, so we can avoid a direct reset of the DRAM. Haven’t started implementing it on the M7 core yet, though.

Thanks a bunch for your help.