XRDC 多核配置 XRDC multi-core configuration

[dingyazhou1]

When I use XRDC to configure a peripheral, whether the same peripheral can be configured to be accessed by multiple cores. This peripheral is read by multiple cores, but not written by multiple cores.

[Daniel-Aguirre]

Hi,

You say that you configure a peripheral to be accessed by multiple bus master and none can write to it? This may be related to the access policy you have defined. Have you verified with a single master?

Also, can you verify what access policy you have defined for your specific peripheral? Should be the DxACP bits [Page 501, S32G2 Reference Manual, Rev. 6, 11/2022].

We also recommend looking into the "AN13024 - S32G Extended Resource Domain Controller (XRDC)" available under the S32G2 product page (link: S32G2 Safe and Secure Vehicle Network Processor | NXP Semiconductors), given it gives more insight into the XRDC module.

Please, let us know.