I am currently working on the A53 core with Yocto BSP 42, and during the compilation process, I observed the following image layout details in the log.do_compile file :
Image Layout
DCD: Offset: 0x200 Size: 0x1c
IVT: Offset: 0x1000 Size: 0x100
HSE Firmware: Offset: 0x1200
HSE SYS Image: Offset: 0x62400 Size: 0xc000
AppBootCode Header: Offset: 0x6e400 Size: 0x40
Application: Offset: 0x6e440 Size: 0x2f800
Boot Core: A53_0
IVT Location: SD/eMMC
Load address: 0x346062c0
Entry point: 0x34610000
Could you kindly help me understand the following:
- Which file or configuration in the Yocto build system is responsible for generating or computing this image layout?
- How can I locate and modify the source file(s) that define these offsets, sizes, and other parameters?
Your guidance on this matter will be greatly appreciated.
Thank you in advance for your support!