The PFE2 on the S32G274 is not functioning.

[LB666]

Hello, we use S32g274A chip with PFE as the master working on core A. PFE2 is configured in RMII mode and connected to the 4G module through MAC to MAC direct connection. We have verified that the hardware wiring is correct. The BSP version we are using is BSP39, and the image is compiled through yocto. When Linux starts up, the following error will be generated:

[    7.805990] pfeng 46000000.pfe: PFEng ethernet driver loading ...

[    7.806012] pfeng 46000000.pfe: Version: 1.6.0

[    7.806017] pfeng 46000000.pfe: Driver commit hash: M4_DRIVER_COMMIT_HASH

[    7.806022] pfeng 46000000.pfe: Multi instance support: disabled (standalone)

[    7.806027] pfeng 46000000.pfe: Compiled by: 11.4.0

[    7.806066] pfeng 46000000.pfe: Cbus addr 0x46000000 size 0x1000000

[    7.806079] pfeng 46000000.pfe: nxp,fw-class-name: s32g_pfe_class.fw

[    7.806087] pfeng 46000000.pfe: nxp,fw-util-name: s32g_pfe_util.fw

[    7.806151] pfeng 46000000.pfe: netif name: pfe0

[    7.806161] pfeng 46000000.pfe: DT mac addr: 00:04:9f:be:ef:00

[    7.806171] pfeng 46000000.pfe: netif(pfe0) linked phyif: 0

[    7.806179] pfeng 46000000.pfe: netif(pfe0) mode: std

[    7.806194] pfeng 46000000.pfe: netif(pfe0) HIFs: count 1 map 01

[    7.806211] pfeng 46000000.pfe: EMAC0 interface mode: 4

[    7.806400] pfeng 46000000.pfe: netif name: pfe1

[    7.806409] pfeng 46000000.pfe: DT mac addr: 00:04:9f:be:ef:01

[    7.806416] pfeng 46000000.pfe: netif(pfe1) linked phyif: 1

[    7.806422] pfeng 46000000.pfe: netif(pfe1) mode: std

[    7.806439] pfeng 46000000.pfe: netif(pfe1) HIFs: count 1 map 02

[    7.806451] pfeng 46000000.pfe: EMAC1 interface mode: 4

[    7.806552] pfeng 46000000.pfe: netif name: pfe2

[    7.806560] pfeng 46000000.pfe: DT mac addr: 00:04:9f:be:ef:02

[    7.806567] pfeng 46000000.pfe: netif(pfe2) linked phyif: 2

[    7.806574] pfeng 46000000.pfe: netif(pfe2) mode: std

[    7.806589] pfeng 46000000.pfe: netif(pfe2) HIFs: count 1 map 04

[    7.806599] pfeng 46000000.pfe: EMAC2 interface mode: 7

[    7.806622] pfeng 46000000.pfe: HIF channels mask: 0x0007

[    7.806669] pfeng 46000000.pfe: PFE port coherency enabled, mask 0x1e

[    7.807089] pfeng 46000000.pfe: Clocks: sys=300MHz pe=600MHz

[    7.811097] pfeng 46000000.pfe: Interface selected: EMAC0: 0x4 EMAC1: 0x4 EMAC2: 0x7

[    7.811319] pfeng 46000000.pfe: PFE controller reset done

[    7.811479] pfeng 46000000.pfe: TX clock on EMAC0 for interface sgmii installed

[    7.811542] pfeng 46000000.pfe: RX clock on EMAC0 for interface sgmii installed

[    7.811624] pfeng 46000000.pfe: TX clock on EMAC1 for interface sgmii installed

[    7.811678] pfeng 46000000.pfe: RX clock on EMAC1 for interface sgmii installed

[    7.811764] pfeng 46000000.pfe: ERR: (DRIVER) event 1 - Driver runtime error: [pfeng-drv.c:546] Failed to enable TX clocks on EMAC2 for interface rmii. Error -5

[    7.811844] pfeng 46000000.pfe: Defer enabling of RX clock on EMAC2 for interface rmii (ret: -5)

[ 7.812039] pfeng 46000000.pfe: assigned reserved memory node pfebufs@34000000

[ 7.812094] pfeng 46000000.pfe: assigned reserved memory node pfebufs@34080000

[ 7.812211] pfeng 46000000.pfe: assigned reserved memory node pfebufs@83200000

[ 7.812255] pfeng 46000000.pfe: assigned reserved memory node pfebufs@835e0000

[ 7.818573] pfeng 46000000.pfe: Firmware: CLASS s32g_pfe_class.fw [45040 bytes]

[ 7.818598] pfeng 46000000.pfe: Firmware: UTIL s32g_pfe_util.fw [23252 bytes]

[ 7.818635] pfeng 46000000.pfe: PFE CBUS p0x46000000 mapped @ v0xffffffc00a000000 (0x1000000 bytes)

[ 7.818648] pfeng 46000000.pfe: Silicon S32G2

[ 7.819751] pfeng 46000000.pfe: PFE_ERRORS:Parity instance created

[ 7.819764] pfeng 46000000.pfe: PFE_ERRORS:Watchdog instance created

[ 7.819774] pfeng 46000000.pfe: BMU1 buffer base: p0xc0000000

[ 7.819879] pfeng 46000000.pfe: BMU2 buffer base: p0x34000000 (0x80000 bytes)

[ 7.821266] pfeng 46000000.pfe: register IRQ 72 by name 'PFE BMU IRQ'

[ 7.821541] pfeng 46000000.pfe: Firmware .elf detected

[ 7.821555] pfeng 46000000.pfe: Uploading CLASS firmware

[ 7.821564] pfeng 46000000.pfe: Selected FW loading OPs to load 8 PEs in parallel

[ 7.821565] pfeng 46000000.pfe: BMU_EMPTY_INT (BMU @ p0x(____ptrval____)). Pool ready.

[ 7.821579] pfeng 46000000.pfe: BMU_EMPTY_INT (BMU @ p0x(____ptrval____)). Pool ready.

[ 7.898266] pfeng 46000000.pfe: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8"

[ 7.918072] pfeng 46000000.pfe: [FW VERSION] 1.8.0, Build: Nov 16 2023, 07:46:11 (nogitaaa), ID: 0x31454650

[ 7.918465] pfeng 46000000.pfe: EMAC timestamp external mode bitmap: 0

[ 7.918593] pfeng 46000000.pfe: register IRQ 73 by name 'PFE UTIL IRQ'

[ 7.955022] pfeng 46000000.pfe: Uploading UTIL firmware

[ 7.955047] pfeng 46000000.pfe: Selected FW loading OPs to load 1 PEs in parallel

[ 7.957643] pfeng 46000000.pfe: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8"

[ 7.958723] pfeng 46000000.pfe: FW feature: drv_run_on_g3

[ 7.958734] pfeng 46000000.pfe: FW feature: jumbo_frames

[ 7.958740] pfeng 46000000.pfe: FW feature: software_vlan_table

[ 7.958746] pfeng 46000000.pfe: FW feature: timestamping

[ 7.958751] pfeng 46000000.pfe: FW feature: qos_mapping

[ 7.958757] pfeng 46000000.pfe: FW feature: core_functionality

[ 7.958762] pfeng 46000000.pfe: FW feature: extended_features

[ 7.958769] pfeng 46000000.pfe: FW feature: flexible_router

[ 7.958774] pfeng 46000000.pfe: FW feature: validate_hif_csum

[ 7.958780] pfeng 46000000.pfe: FW feature: err051211_workaround

[ 7.958786] pfeng 46000000.pfe: FW feature: IPsec

[ 7.958791] pfeng 46000000.pfe: FW feature: l2_bridge_aging

[ 7.958796] pfeng 46000000.pfe: FW feature: receive_malformed

[ 7.958802] pfeng 46000000.pfe: FW feature: ptp_conf_check

[ 7.958807] pfeng 46000000.pfe: FW feature: vlan_conf_check

[ 7.958812] pfeng 46000000.pfe: FW feature: hash_load_spread

[ 7.958818] pfeng 46000000.pfe: FW feature: ingress_vlan

[ 7.958824] pfeng 46000000.pfe: FW feature: safety

[ 7.961345] pfeng 46000000.pfe: VLAN ID incorrect or not set. Using default VLAN ID = 0x01.

[ 7.961366] pfeng 46000000.pfe: VLAN stats size incorrect or not set. Using default VLAN stats size = 20.

[ 7.961468] pfeng 46000000.pfe: Software vlan hash table @ p0x20001278

[ 7.961649] pfeng 46000000.pfe: Fall-back bridge domain @ 0x20000a80 (class)

[ 7.961656] pfeng 46000000.pfe: Default bridge domain @ 0x20000a78 (class)

[ 7.968108] pfeng 46000000.pfe: Routing table created, Hash Table @ p0x34080000, Pool @ p0x34088000 (65536 bytes)

[ 7.968481] pfeng 46000000.pfe: Feature err051211_workaround: DISABLED

[ 7.983509] pfeng 46000000.pfe: MDIO bus 0 disabled: Not found in DT

[ 7.983533] pfeng 46000000.pfe: MDIO bus 1 disabled: Not found in DT

[ 8.058051] mdio_bus PFEng Ethernet MDIO.2: MDIO device at address 0 is missing.

[ 8.058081] pfeng 46000000.pfe: MDIO bus 2 enabled

[ 8.058507] pfeng 46000000.pfe: HIF0 enabled

[ 8.058805] pfeng 46000000.pfe: HIF1 enabled

[ 8.059072] pfeng 46000000.pfe: HIF2 enabled

[ 8.059079] pfeng 46000000.pfe: HIF3 not configured, skipped

[ 8.059197] pfeng 46000000.pfe pfe0 (uninitialized): Subscribe to HIF0

[ 8.059208] pfeng 46000000.pfe pfe0 (uninitialized): Host LLTX disabled

[ 8.059641] pfeng 46000000.pfe pfe0 (uninitialized): Enable HIF0

[ 8.059807] pfeng 46000000.pfe pfe0 (uninitialized): setting MAC addr: 00:04:9f:be:ef:00

[ 8.059845] pfeng 46000000.pfe pfe0 (uninitialized): PTP HW addend 0x80000000, max_adj configured to 46566128 ppb

[ 8.059857] pfeng 46000000.pfe: IEEE1588: Input Clock: 200000000Hz, Output: 100000000Hz, Accuracy: 10.0ns

[ 8.065438] pfeng 46000000.pfe pfe0 (uninitialized): Registered PTP HW clock successfully on EMAC0

[ 8.080137] pfeng 46000000.pfe pfe0: registered

[ 8.081323] pfeng 46000000.pfe pfe1 (uninitialized): Subscribe to HIF1

[ 8.081340] pfeng 46000000.pfe pfe1 (uninitialized): Host LLTX disabled

[ 8.081789] pfeng 46000000.pfe pfe1 (uninitialized): Enable HIF1

[ 8.082328] pfeng 46000000.pfe pfe1 (uninitialized): setting MAC addr: 00:04:9f:be:ef:01

[ 8.082363] pfeng 46000000.pfe pfe1 (uninitialized): PTP HW addend 0x80000000, max_adj configured to 46566128 ppb

[ 8.082378] pfeng 46000000.pfe: IEEE1588: Input Clock: 200000000Hz, Output: 100000000Hz, Accuracy: 10.0ns

[ 8.088722] pfeng 46000000.pfe pfe1 (uninitialized): Registered PTP HW clock successfully on EMAC1

[ 8.091245] pfeng 46000000.pfe pfe1: registered

[ 8.091341] pfeng 46000000.pfe pfe2 (uninitialized): Subscribe to HIF2

[ 8.091351] pfeng 46000000.pfe pfe2 (uninitialized): Host LLTX disabled

[ 8.091798] pfeng 46000000.pfe pfe2 (uninitialized): Enable HIF2

[ 8.091965] pfeng 46000000.pfe pfe2 (uninitialized): setting MAC addr: 00:04:9f:be:ef:02

[ 8.092000] pfeng 46000000.pfe pfe2 (uninitialized): PTP HW addend 0x80000000, max_adj configured to 46566128 ppb

[ 8.092012] pfeng 46000000.pfe: IEEE1588: Input Clock: 200000000Hz, Output: 100000000Hz, Accuracy: 10.0ns

[ 8.093168] pfeng 46000000.pfe pfe2 (uninitialized): Registered PTP HW clock successfully on EMAC2

[ 8.097509] pfeng 46000000.pfe pfe2: registered

[ 9.164868] random: dbus-daemon: uninitialized urandom read (12 bytes read)

[ 9.186468] random: dbus-daemon: uninitialized urandom read (12 bytes read)

[ 9.231066] random: rngd: uninitialized urandom read (4 bytes read)

[ 9.231658] random: crng init done

[ 9.231662] random: 2 urandom warning(s) missed due to ratelimiting

[ 9.580247] pfeng 46000000.pfe: HIF2 started

[ 9.580276] pfeng 46000000.pfe pfe2: configuring for fixed/rmii link mode

[ 9.580538] pfeng 46000000.pfe pfe2: Link is Up - 100Mbps/Full - flow control off

[ 9.580853] pfeng 46000000.pfe: ERR: (DRIVER) event 1 - Driver runtime error: [pfeng-netif.c:1385] Failed to enable RX clock on EMAC2 for interface rmii (err -5)

[ 9.581665] pfeng 46000000.pfe: HIF1 started

[ 9.581684] pfeng 46000000.pfe pfe1: configuring for fixed/sgmii link mode

[ 9.582026] pfeng 46000000.pfe pfe1: Link is Up - 1Gbps/Full - flow control off

[ 9.582995] pfeng 46000000.pfe: HIF0 started

[ 9.583017] pfeng 46000000.pfe pfe0: configuring for fixed/sgmii link mode

[ 9.583358] pfeng 46000000.pfe pfe0: Link is Up - 1Gbps/Full - flow control off

Could you please help me solve this error? Thank you

[Joey_z]

hi,LB666

Thank you for contacting us.

Do you use the RDB2 development board or the custom version? According to the information you provided, there was a problem when attempting to enable the TX clock of EMAC2.

BR

Joey

[LB666]

We are using a customized board, and we have already achieved communication between PFE2 and 4G modules based on RMII mode by running PFE Master on the M core. Now we want to run PFE Master on the A core to achieve communication between PFE2 and 4G modules. We have only made the following modifications in the device tree of ATF and Linux:

&pfe_netif2 {

-    phy-mode = "rgmii-id";

-    phy-handle = <&pfe_mdio_b_phy4>;

+    phy-mode = "rmii";

+    fixed-link {

+    speed = <100>;

+    full-duplex;

+       };

 };

We are not very familiar with ATF and Linux code. Can you let us know if we can solve the above errors?

[Joey_z]

hi，LB666

Which the type of PHY is you using? Refer to the BSP user manual, an external PHY works as external 50MHz clock source for PFE_EMAC_2.

I think you should father check the setting of PFE_MAC2_TX_CLK  in A core.

BR

Joey