Single Rank DRAM Setup in AT-F

[minersrevolt]

I am trying to set up a Single Rank DRAM (MT53E512M32D1ZW) in a custom S32G3 based board. It is failing the ddr initialization in the Arm Trusted Firmware (AT-F) here.

I have identified a few places in the code base where some logical changes should be made (below) but cannot get the device to initialize. I am also seeing some PLL registers that are being written to that I cannot find in the S32G3 Reference Manual or in the ARM Reference Manual.

Changes made to the AT-F in this file,

diff --git a/drivers/nxp/s32/ddr/s32g3/ddrc_cfg.c b/drivers/nxp/s32/ddr/s32g3/ddrc_cfg.c
index e8a511816..d833a5f33 100644
--- a/drivers/nxp/s32/ddr/s32g3/ddrc_cfg.c
+++ b/drivers/nxp/s32/ddr/s32g3/ddrc_cfg.c
@@ -31,8 +31,10 @@
 #include "ddr_init.h"
 
 struct regconf ddrc_cfg[] = {
-       {0x403c0000, 0x83080020U},
-       {0x403c0010, 0x00000030U},
+       /* {0x403c0000, 0x83080020U}, // MSTR reg 2 rank */
+       {0x403c0000, 0x81080020U}, // MSTR reg 1 rank
+       /* {0x403c0010, 0x00000030U}, // MRCTRL0 reg 2 rank */
+       {0x403c0010, 0x00000010U}, // MRCTRL0 reg 1 rank
        {0x403c0014, 0x00000000U},
        {0x403c001c, 0x00000000U},
        {0x403c0020, 0x00001203U},

Additionally the PLL is being configured here and here and I cannot find references to the registers being used anywhere.

I am still going through the DDRC register set to see if there is anything else to identify but would like to know if anyone here may know what specifically needs to change to configure this.

[chenyin_h]

Hello, @minersrevolt 

Thanks for the reply.

From my opinion, you may modify the chip select to 1.

BR

Chenyin

[minersrevolt]

Hey @chenyin_h 

I was able to succesfully run the ddr initialization test using the tool. I imported the generated output files to the AT-F and still see DDR Initialization failure after updating the AT-F. I attached the output files from the DDR Test along with the log and test results html.

I ran the same test on an RDB3 evaluation board and confirmed that the log the tool generates is identical.

Any ideas why this wouldn't work?

[chenyin_h · Accepted solution]

Hello, @minersrevolt 

Thanks for your questions.

Overall, under this community, we don't fully support custom designs. We do apologize.

Regarding to change to support new DDR parts like single rank one, from my opinion, you may not need to directly change the ddr related code based on BSP release, I have the following suggestions for your reference:

1. S32G3 can interface single rank memory
2. Use the DDR tool in S32DS to do corresponding training and generate corresponding configuration files, Check the generated code and the original code under /arm-trusted-firmware/drivers/nxp/s32/ddr, drivers/nxp/s32/ddr/s32g3, /include/drivers/nxp/s32/ddr
3. Copy the new generated code to the directory above, some minor modification may need accordingly.
4. Then recompile the ATF to try booting the your board.

BR

Chenyin

[minersrevolt]

Hey @chenyin_h I was able to get the S32DS DRAM test tool up and running. Looking at the DDR View tab I do not see any option for selecting the rank and assume it is defaulting to dual rank. Is there a way to be explicit about single rank?

[minersrevolt]

The intent to modify the PLL settings is to see if I can lower rate to fight any potential trace issues on the PCBA.

[minersrevolt]

Error from BL2,

NOTICE:  Reset status: Power-On Reset                                                        
INFO:    BL2: FIP offset = 0x21240                                                           
INFO:    Switch to 50 MHz SD frequency (High Speed Mode)                                     
INFO:    Image 3 spec: offset=0x6b190 length=0x46800                                         
INFO:    Image 5 spec: offset=0xb1830 length=0xdd600                                         
INFO:    Complete PMIC setup                                                                 
ERROR:   Failed to configure the DDR subsystem                                               
BACKTRACE: START: bl2_el3_plat_arch_setup                                                    
0: EL3: 0x34312184                                                                           
1: EL3: 0x3431108c                                                                           
2: EL3: 0x34311408                                                                           
3: EL3: 0x343020e0                                                                           
BACKTRACE: END: bl2_el3_plat_arch_setup                                                      
PANIC at PC : 0x0000000034311094