Hi,
Currently, Executing shutdown scheck AhbTest_CM7_0 Test(cm7_0_tcm_ahb
_slice_err_inj_0).
I have observed that the respective test is injecting a fault at u32CtrlRegAddr = 0x4007CA28 with mask u32CtrlRegMask = 0x1, but it's failing at sCheck_DetectAndClearFault.
I have observed that the status register, u32StatRegAddr = 0x4007CAFC, with mask u32StatRegMask = 0x00200000, doesn't get updated during the test.
It can refer to the snippet.
Q1. Should the status register update the moment the control register is updated with fault injection?
Q2. any prerequisites that shall be implemented?
Regards,
Irshad
Hello @Irshad2225,
Thanks for reaching out to us. Regarding your problem, Can you share the list of errors you are passing in the first argument of sCheck_AhbTest_CM7? This is, sCheck_ErrorContainerType * pErrorContainer, I ask this, because as per your post, you expect the bit 0x0002_0000 (bit 17), which is a read only bit (with write-1-clear config) in the Cortex-M7 AXI Parity Error and AHBP Gasket Error Alarm (CM7_AXI_AHBP_GASKET_ERROR_ALARM) register:
Can you confirm if your configuration is valid?
One other thing that may help us is testing the same AHB test configuration but instead of performing it during shutdown, run it during boot or normal operation, in the past I have seen some test fail only during shutdown, please test that setup and let me know if you see the same behavior.
As a side note, this are the prerequisites for the AHB CM7 test:
Please check if they are met in your setup.
Thanks in advance
Hello @Irshad2225
Thanks for the information. However, I still don't fully understand your request, After reviweing the code I don't see why are you expecting the register at 0x4007CAFC (CM7_AXI_AHBP_GASKET_ERROR_ALARM) to set its 17th bit:
that part of the register is write-1-clear, therefore, "writing 1" to the register, it will be cleared.
Which is the behavior your are seeing correct?
Let me know if I am understanding your explanation correctly.
