Fls_TS_T40D11M30I2R0
static void Fls_PinSetup(void)
{
IP_SIUL2_0->MSCR[85] = 0x00280021U; /*QSPI_A[0]*/
IP_SIUL2_0->MSCR[86] = 0x00280021U; /*QSPI_A[1]*/
IP_SIUL2_0->MSCR[87] = 0x00280021U; /*QSPI_A[2]*/
IP_SIUL2_0->MSCR[88] = 0x00280021U; /*QSPI_A[3]*/
IP_SIUL2_0->MSCR[89] = 0x00280021U; /*QSPI_A[4]*/
IP_SIUL2_0->MSCR[90] = 0x00280021U; /*QSPI_A[5]*/
IP_SIUL2_0->MSCR[91] = 0x00280021U; /*QSPI_A[6]*/
IP_SIUL2_0->MSCR[92] = 0x00280021U; /*QSPI_A[7]*/
IP_SIUL2_0->MSCR[93] = 0x00280021U; /*QSPI_A Data strobe*/
IP_SIUL2_0->MSCR[96] = 0x00200021U; /*QSPI_A Serial Clock*/
IP_SIUL2_0->MSCR[97] = 0x00200021U; /*QSPI_A Serial Clock*/
IP_SIUL2_0->MSCR[98] = 0x00200021U; /*QSPI_A Serial Clock*/
IP_SIUL2_0->MSCR[99] = 0x00200021U; /*QSPI_A Serial Clock*/
IP_SIUL2_0->MSCR[100] = 0x00203021U; /*QSPI_A Chip select*/
IP_SIUL2_0->MSCR[101] = 0x00203021U; /*QSPI_A Chip select*/
IP_SIUL2_0->IMCR[28] = 0x00000002;
IP_SIUL2_0->IMCR[29] = 0x00000002;
IP_SIUL2_0->IMCR[30] = 0x00000002;
IP_SIUL2_0->IMCR[31] = 0x00000002;
IP_SIUL2_0->IMCR[32] = 0x00000002;
IP_SIUL2_0->IMCR[33] = 0x00000002;
IP_SIUL2_0->IMCR[34] = 0x00000002;
IP_SIUL2_0->IMCR[35] = 0x00000002;
IP_SIUL2_0->IMCR[36] = 0x00000002;
/*QSPI_A INTERRUPT: ECC error signal, Flash Memory A drives this signal to active low value in case of an ECC error */
IP_SIUL2_0->MSCR[94] = 0x00083020; /* Disable OBE; Enable IBE; Enable pull-up */
IP_SIUL2_0->IMCR[37] = 0x00000002;
}