S32G399A - MDIO configuration in the Device Tree

[GuilhermeS32G3]

Dear NXP fellows,

I am using BSP41.0 and a board based on S32G399ARDB3.

Looking at the Linux Kernel Device Tree Configuration file, I see this PFE MDIO2 definition:

&pfe_mdio2 {
	/* AR8035 */
	pfe_mdio_b_phy4: ethernet-phy@4 {
		reg = <4>;
	};
	/* SJA1110's phys: 0x09-0x0e */
};

Then I see this PFE_MAC2 interface definition:

&pfe_netif2 {
	phy-mode = "rgmii-id";
	phy-handle = <&pfe_mdio_b_phy4>;
};

It uses as PHY handle the pfe_mdio_b_phy4 declared above.

What concerns me are the comments.

According to the User Guide we have this configuration as default:

In this configuration, the PFE_MAC2 interface is connected through RGMII to the PHY Micrel KSZ9031. The PHY Atheros AR8035 is connected through RGMII to the ports 2 and 3 of the SJA1110 switch. The switch is accessed by default through SGMII in its port 4 by PFE_MAC0.

So what is the relation between PFE MDIO2 and the SJA1110? Why is the SJA1110 PHY MDIOs in PFE_MAC2 interface if the PFE_MAC2 is not even connected to the switch?

Thank you very much for the support,

Best regards

Guilherme

[alejandro_e]

Hello @GuilhermeS32G3,

I will try to reach the internal team in charge of the component and come back to you. I appreciate your patience.

Best regards

[alejandro_e]

hello @GuilhermeS32G3 ,

I have received an answer from the internal team:

"

There are two MDIO interfaces in SJA1110, the one is SMI_OUT_MDC and SMI_OUT_MDIO, the SMI_OUT interface is intended to be used to configure external PHY devices from the SJA1110 internal M7 core. The other is SMI_AP_MDC and SMI_AP_MDIO, The SMI access point (SMI-AP) interface allows S32G to access SJA1110 internal 100BASE-T1 PHYs. From the schematics of SJA1110 part in S32G-RDB3 board, the SMI_OUT_MDC and SMI_OUT_MDIO connected to 2 external PHYs  AR8035, and PFE_MDIO2 connected to SMI-AP of SJA1110, so that S32G could access the internal SJA1110 100BASE-T1 PHYs (address from 0x09~0x0e):

Notes: the phy address in the node pfe_mdio2 of device tree is really for pfe2 PHY KSZ9031.

"

Let me know if this answers your question

[GuilhermeS32G3]

Hello @alejandro_e ,

Thank you very much for your reply,

Yes, I think it answers my question, and it complements Pavel's reply in my other question. In the default case (AR8035 connected to the SJA1110) there is no need to configure the AR8035 PHY in the Linux Kernel Device Tree, as this is responsibility of the SJA1110 firmware.

As we are discussing this, another question arises.

Still in the s32gxxxa-rdb.dtsi file, line 761, it defines the spi5 configuration. Within spi5, there are 3 nodes relative to SJA1110: sja1110-uc@0  (line 772), sja1110-sw@1 (line 780), and ethernet-switch@1  (line 795).  The former two are the SPI interfaces for reading the SJA1110 microcontroller firmware and switch configuration. But the latter one, ethernet-switch@1,  is an alternative, that requires the other two to be disabled before enabling it.

I would like to know in which cases ethernet-switch@1 is used? If I enable this node, can I configure the PHYs connected to Ports 2 and 3 in the same way as the PHY connected to pfe_netif2?

Best regards,

Guilherme

[alejandro_e · Accepted solution]

Hello @GuilhermeS32G3 ,

I have received the following answer from the internal team:

"

Yes, if ethernet-switch@1 is enable ,then the PHYs driver of Port 2 &3, and 6 * 100BaseT Ports of SJA1110 will be loaded when Linux kernel boots and The ports could be viewed with command "ifconfig -a"

"

Let me know if this information solves your questions.

[GuilhermeS32G3]

Hello @alejandro_e ,

Thank you for your reply.

Yes, this certainly worth a try.

Best regards,

Guilherme