S32G399 PCIe cannot send TLP packets

[LONGGANGSU]

As shown in the figure, please help me. Currently, I am using the S32G399A chip and connecting it to an FPGA via the PCIe interface. In this configuration, the S32G399A acts as the RC and the FPGA acts as the EP. The problem I am encountering now is that the config space of the FPGA can be accessed, but the mem space of bar0 cannot trigger TLP.
The following figure shows the information printed by "dmesg" in the operating system. In the "outbound" section, it shows 6OB and 4IB. How should this outbound and inbound be configured and where should it be configured?

Also, what do Original Address  Base Address  Target Address represent respectively?

[chenyin_h]

Hello, @LONGGANGSU 
Thanks for the reply.

I found this issue is also introduced via other channel, help it there directly.

BR

Chenyin 

[LONGGANGSU]

Does it mean to solve it through FAE?@cehnyin_h

[chenyin_h]

Hello, @LONGGANGSU 

Thanks for the post.

1. Seems you are working with BSP, which version?

2. Which serdes is used for connected to the device, PCIe x1 is used?

3. For the snapshot mentioned, which document it referred to?

BR

Chenyin 

[LONGGANGSU]

1.BSP是43.0

2.是pcie X1。

3.第二张照片是RMS32G3SERDES.pdf，3.10.3章节。