Hi,
Thanks for your feedback.
Below will be some comments on regards of your questions:
1. In this example of the function "Sys_StartSecondaryCores", the macro definition START_CM7_1 is not defined, so how to go about the next steps.
[DA]I: t does seem to be that the enablement of the M7_1 is being done under the Mcu_SetMode(McuModeSettingConf_0); function. This given the following configuration under the Mcu peripheral:

2. According to your explanation just now and the content of the reference manual, can I understand that CM7_1 is enabled by CM7_0, and only the CM7_1 starting address and clock configuration are provided in CM7_0, and then the reset is completed
3. Enabling CM7_2 is the same step as enabling CM7_1
[DA]: We might be misunderstanding, if so we do apologize.
In general, as seen under the flow chart of the RM, you need to provide an address, enable the clock then deassert the reset of the respective core. This enablement flow is the same for all the available cores inside the S32G3 chip [Page 1256, S32G3 Reference Manual, Rev. 4, 02/2024]:
"This sequence can be used to turn on the Cortex-M7 application cores or the Cortex-A53 cluster cores."
Please, let us know.