S32G3 GMAC0 can not attach custom phy

[GG0712]

Hi

I'm currently use S32G3 SoC and S32G399ARDB3 custom board with Auto Linux BSP 35.0.

Our design is SerDes 1 connect to ethernet switch through PCIe.

GMAC0 connect 2 custom phys with address 0x1 and 0x3 through MDC/MDIO.

Ethernet switch connect 2 phys through HSGMII

Ethernet switch can work normally, phy register can access through mdio tool,.

But now gmac0 can not attach to phy, should we modify gmac driver ?

root@s32g399ardb3:~# dmesg | grep "s32cc-dwmac"
[ 0.954524] s32cc-dwmac 4033c000.ethernet: IRQ eth_wake_irq not found
[ 0.961096] s32cc-dwmac 4033c000.ethernet: IRQ eth_lpi not found
[ 0.967351] s32cc-dwmac 4033c000.ethernet: no reset control found
[ 0.973685] s32cc-dwmac 4033c000.ethernet: phy mode set to RGMII
[ 0.979917] s32cc-dwmac 4033c000.ethernet: User ID: 0x10, Synopsys ID: 0x52
[ 0.987025] s32cc-dwmac 4033c000.ethernet: DWMAC4/5
[ 0.992094] s32cc-dwmac 4033c000.ethernet: DMA HW capability register supported
[ 0.999548] s32cc-dwmac 4033c000.ethernet: RX Checksum Offload Engine supported
[ 1.007002] s32cc-dwmac 4033c000.ethernet: TX Checksum insertion supported
[ 1.014017] s32cc-dwmac 4033c000.ethernet: Wake-Up On Lan supported
[ 1.020443] s32cc-dwmac 4033c000.ethernet: Enabled workarounds for s32g274a platform
[ 1.028342] s32cc-dwmac 4033c000.ethernet: Enable RX Mitigation via HW Watchdog Timer
[ 1.036336] s32cc-dwmac 4033c000.ethernet: device MAC address 3e:c7:70:9f:25:b4
[ 1.043795] s32cc-dwmac 4033c000.ethernet: Enabled Flow TC (entries=8)
[ 1.050459] s32cc-dwmac 4033c000.ethernet: Enabling HW TC (entries=256, max_off=256)
[ 1.058358] s32cc-dwmac 4033c000.ethernet: Using 32 bits DMA width
[ 6.308041] s32cc-dwmac 4033c000.ethernet eth0: validation of rgmii-id with support 0000000,00000000,000062c0 and advertisement 0000000,00000000,000062c0 failed: -22
[ 6.308076] s32cc-dwmac 4033c000.ethernet eth0: no phy at addr -1
[ 6.308082] s32cc-dwmac 4033c000.ethernet eth0: stmmac_open: Cannot attach to PHY (error: -19)

Here is our device tree about phy config on s32gxxxardb.dtsi

 &gmac0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&gmac0rgmiia_pins>, <&gmac0mdioa_pins>;
	phy-handle = <&gmac_mdio_a_phy1>;
	phy-mode = "rgmii-id";
};

&gmac0_mdio {
	/* KSZ9031 GMAC */
	// gmac_mdio_a_phy0: ethernet-phy@0 {
	// 	reg = <0>;
	// };
	gmac_mdio_a_phy1: ethernet-phy@1 {
		reg = <1>;
	};
	gmac_mdio_a_phy3: ethernet-phy@3 {
		reg = <3>;
	};
};

[alejandro_e]

Hello @GG0712,

Thanks for contacting NXP support.  About your problem, can you share the following information?

• Can you share your schematics or a block diagram of the S32G3-SWITCH-PHYs connections? This is to better understand your setup.
• Can you share the part number of the switch you are using?
• Can you share the part number of the PHYs you are using?
• Can you please confirm if you are using a custom board or a reference design board (RDB3)? This is, is you board provided by NXP or designed by your company?
• Is there a reason you are using BSP35? This being a rather old version, could present some unexpected and untested behaviors. 

Thanks for the information in advance.

If you don't want to share sensitive information using this public community, you can open a support ticket using the nxp page: 

 

[GG0712]

Hi @alejandro_e 

My ticket support case id is 00689830

Thanks.

[alejandro_e]

Hello @GG0712,

Please check my answers in the support ticket.

Thanks.