S32G274A SGMII Interface - Clock

[gopalakrishna]

Hi,

One of custom board design we are using S32G274A processor, a 1000BASE-T1 PHY interfacing over the SGMII interface.

PHY Interface to Processor:

SERDES1_LANE1 (PFE1)

SERDES1_LANE0 (PFE0)

An external clock generator (Part No : CDCE6214TWRGETQ1) is use for PHY Ref Clock input.

Is it possible to use internal clock instated of external clock generator?

Thank you.

Regards,

Gopala

[Daniel-Aguirre]

Hi,

For SerDes_1 Mode 4 (which is what we understand you are looking for), it seems that all available configurations we can find use an external clock. We mainly see the internal clock being used when only 1 lane is being used.

Still, which BSP version are you using?

Please, let us know.

[gopalakrishna]

Hi Daniel,

Thanks for your support!

BSP version: 31 

We need your support regarding the SGMII interface of PHY Broadcom part (Part No: BCM89885MA0BWMLG)

Here is the details of SerDes lines using to interface the PHY.

SERDES1_LANE1 (PFE1)

SERDES 0 _LANE1 (PFE 2)

SERDES1_LANE 0 (PFE 0)

The MDC and MDIO lines are common for SERDES1_LANE 0 (PFE 0), SERDES 0 _LANE1 (PFE 2).

As of now, we are able to detect the PHY but link is not happening.

From our team, Shwetha Naik is communicating with you and we need to fix this issue on priority.

from PHY side, the strap signal status, HW configurations and voltage rails are as per datasheet recommended.

Need your quick support to PHY interface and working.

[gopalakrishna]

Hi,

BSP Version: 31

Regards,

Gopala

[Daniel-Aguirre]

Hi,

Thanks for your feedback. For the information available to us, it seems that our previous comment is still valid, where the configuration examples use the external clock for the specific SerDes mode.

Please, let us know.