S32G2 Errata ERR050166

[lvaynberg]

Errata ERR050166 workaround states that "SW must write these registers in order to clear/change their values". Where can I get the list of the register writes and values that are needed to be performed?

The errata furthermore states "If LBIST is run on this domain, SW must make sure to re-program these registers prior to starting transactions through the NOC to make sure they are configured properly."

Which NOC does this effect?

Is it feasible that running software on the startup M7 core does not generate any traffic to this NOC?

[Daniel-Aguirre]

Hi,

The ERRATA tells which registers are only reset by a destructive reset. The following is told:

"The QoS Generator registers as well as the safe_partial_pfe_main and safe_partial_reset0_main Resilience fault controller
registers are only reset via a destructive reset. This means their values will not change on a functional reset. "

For the QoS Generator, we find the following information inside the S32G2 Reference Manual [Page 128, S32G2 Reference Manual, Rev. 7, February 2023]:

"There are QoS generators implemented for CAIU0 and CAIU1 inside CCTI. They operate in fixed mode, that is, assign fixed urgency value to packets"

As for the other 2 mentioned registers, these are part of the SPD package, in which the definitions are provided inside the same package.

As for NoC, it should be the one being used by the domain in which LBIST is configured.

As for the feasibility, we have not received any situations in which running the startup code under the M7 causes this behavior. Even the expected boot sequence for S32G platform is to boot-up from the Real Time core (which is M7_0) then start the other applications.

Please, let us know.