Hi,
In one of our development project, we are using NXP S32G2 processor and interfacing with Aurora Trace connector.
On layout point, placement of Aurora Trace connector and signals routing are meeting layout guidelines of Aurora Trace connector (AN12530).
But not clear on length of differential pair. same is compare in RDB2 layout, it is ~1200mils, whereas in our PCB it is ~4500mils Max.
Here is the details about the PCB Layout:
1. No of layers : 10 layers
2. Signals (AUR_TXP2, AUR_TXN2) : Routed in layer 3
3. Signals (AUR_TXP0, AUR_TXN0) : Routed in layer 3
4. Signals (AUR_TXP1, AUR_TXN1) : Routed in layer 1 (Top Layer)
5. Signals (AUR_TXP3, AUR_TXN3) : Routed in layer 1 (Top Layer)
6. Signals (AUR_REF_CLKP, AUR_REF_CLKN) : Routed in layer 3
Attached the images of RDB2 and our PCB layouts for reference.
Query:
1. As signals length is high, Is there any effect on functionality of Aurora interface?.
2. Is it Okay, signals routed inner layers of layout and in multiple layers? (As per AN12530,Preferably on the top or bottom plane of the board).
3. Signal Integrity (SI) to be performed for Aurora signals?


Thank you.
Regards,
Gopala