S32G M7_0 and M7_1 cores run independent / in parallel

[Vijayan_Thangavel]

hello, 

2 VMs are present in my system, on VM0 for Core0 (M7_0) and VM1 for Core1(M7_1)

Able to flash those 2 elf files on SRAM. VM0 is running fine. but  M7_1 (VM1) is not running properly. 

when we check registers, the Program counter is referring only VM0 memory address.

Do i need to taken care any Register settings and boot up sequence to invoke M7_1 core. 

kindly support on the same. if you need more info kindly revert. 

thanks

[Vijayan_Thangavel]

hello Daniel,

thank you for your feedback. 

Is it possible to run the M7_0 and M7_1 independently by settings the proper register settings?

I will check the documents and get back to you, incase any confusions. 

thanks a lot. 

[Daniel-Aguirre]

Hi,

All cores inside the S32G platform should be able to run independently. As you are saying, the correct configurations are needed for them to be able to run.

As a note, care should be taken with the sharing of resources, since this should also be handled by the developer.

Please, let us know.

[Vijayan_Thangavel]

Actually i have seen the referred document already. but in that document they are referring more on S32G tool. right now we are not implementing boot. just want to flash in the SRAM directly on M7_0 and M7_1 , and wanted to invoke the cores and make parallel run. is it possible?
latest issue: Core1 Program counter is referring Core0 program counter. seems IVT and CSR , CCR address to be set properly. could you please share snap/list of M7_1 specific registers if possible?

[Vijayan_Thangavel]

as per my debugging i need to set this Registers and values I feel. could you please clarify these values for Core1( M7_1). meantime, we are not using A53 cluster right now.

[Daniel-Aguirre]

Hi,

The specific registers for M7_1 should be provided under Chapter 32 of the reference manual [Page 1219, S32G2 Reference Manual, Rev. 6, 11/2022]. We recommend looking into Figure 152 from the Reference Manual [Page 1083, S32G2 Reference Manual, Rev. 6, 11/2022], since the flow diagram shows the different registers that are needed in order to boot an additional core.

Please, let us know.

[Daniel-Aguirre]

Hi,

Thanks for your feedback. If you need to run M7_0 and M7_1 (from external memory) at the same time, a bootloader is needed. NXP provides this bootloader and AN13750 provides steps on how to configure the provided NXP bootloader.

You could debug both applications, but scripts are needed to be able to configure the platform to both 2 or more cores. Under the S32 Debug Probe, the scripts are provided once S32 Design Studio is installed. For Lauterbach, scripts should also be provided for this, but we recommend looking with them this situation.

Please, let us know.

[Daniel-Aguirre]

Hi,

We understand that you are trying to implement a multicore application under the S32G2 platform. If so, we recommend reading AN13750 since this is the only multicore demo available under S32G2. The files needed are available under the S32G2 product page (link: S32G2 Safe and Secure Vehicle Network Processor | NXP Semiconductors) in the "Documentation" section, both the AN13750 and the AN13750SW.

Inside the AN13750, all steps needed to implement a multicore application are provided. The patches and projects (not including the bootloader, which AN13750 tells where to find it) required are provided in the AN13750SW.

S32G2 has a kind of unique boot process, in which the integrated BootROM only starts 1 core, all the other cores have to be configured and started from this single online core, which has to be done by the developer. We can recommend looking into the AN12422 available under the S32G2 product page (link above) for an overview on the S32G2 boot process.

Also, Figure 152 [Page 1083, S32G2 Reference Manual, Rev. 6, 11/2022] inside the Reference Manual provides a sequence on how to start additional cores.

We can also recommend reading "Chapter 32 Mode Entry Module (MC_ME)"  [Page 1219, S32G2 Reference Manual, Rev. 6, 11/2022] which provides a little more detail on the required registers for a multicore boot (on regards of clock enable, start address, etc...).

Please, let us know if there is anything else we can help you with.