Quad SPI and QSPI_SRE

[harry_choi]

Hello Community,

I would like to use Quad SPI but I have some question about it.

Per SoC datasheet, I have to set QSPI_SRE[2:0]=110b to use Quad SPI but the value comes from BOOT_CFG3[7:5].

If we didn't fuse the BOOT_CFG3[7:5] before, then the value will be always '000'.

In this case, how I can boot from Quad SPI?

Will bootrom set 110b to the QSPI_SRE during initialization of QSPI controller?

Thanks,

Harry

[Bulat]

It is BootROM who configures the QSPI pads to SRE value of '000' which means maximum slew rate. The idea is to be able to meet the max QSPI freq requirements that can be up to 200MHz. No problem with boot from Quad SPI with this setting.

Although not required, but customer can modify pad these settings through the BOOT_CFG3 fuses.

Regards,

Bulat

[harry_choi]

Dear Bulat,

Thanks for your replay.

I saw that QSPI_SRE should be 110b for Quad Flash in S32G SoC datasheet, but do you mean that I can ignore it and QSPI_SRE=000b will support Quad Flash(not Octa Flash)?

One more question, if I set SRE in BOOT_CFG3 without  setting FUSE_SEL in BOOT_CFG2, then does the BootROM configures QSPI_SRE with default value('000b') or from SRE in BOOT_CFG3?

Best Regards,

Harry

[Bulat · Accepted solution]

Value SRE=000 is required for high QSPI frequencies (166MHz and 200MHz), but yes, it will be functional at lower frequencies as well.

FUSE_SEL should be set to initialize QSPI pads (including SRE) from BOOT_CFG3 register.

Regards,

Bulat