PFE2 in sgmii mode working in kernel but not in u-boot

[khan_misbah]

Hi All,

I am using a custom s32g2 based hardware with PFE2 is connected to serdes0.
Here are my dts setting working in kernel :

&pfe_netif2 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&pfe_mdio_b_phy2>;
managed = "in-band-status";
};

&pfe_mdio2 {
status = "okay";

/* TJA1104B */
pfe_mdio_b_phy2: ethernet-phy@2 {
reg = <27>;
};

};

pfe2mdioa_pins: pfe2mdioa_pins {
pfe2mdioa_grp0 {
pinmux = <S32CC_PINMUX(80, FUNC1)>;
output-enable;
slew-rate = <S32CC_FAST_SLEW_166MHZ>;
};

pfe2mdioa_grp1 {
pinmux = <S32CC_PINMUX(81, FUNC2)>;
output-enable;
input-enable;
slew-rate = <S32CC_FAST_SLEW_166MHZ>;
};

pfe2mdioa_grp2 {
pinmux = <S32CC_PINMUX(877, FUNC2)>;
};
};

The same device tree setting is done in the ATF device tree.
But in the boot loader its giving the below error :

/******************************************************************/

Failed to configure XPCS0_1
Failed to update XPCS1 for SerDes0
Failed to configure XPCS1_1
Failed to update XPCS1 for SerDes1
In:    serial@401c8000
Out:   serial@401c8000
Err:   serial@401c8000
Board revision: RDB2
Net:
Found PFE version 0x50300 (S32G2)
pfeng pfeng-base: Uploading CLASS firmware
pfeng pfeng-base: EMAC0 block was initialized
pfeng pfeng-base: EMAC1 block was initialized
pfeng pfeng-base: EMAC2 block was initialized
pfeng pfeng-base: Enabling the CLASS block
pfeng pfeng-base: PFE Platform started successfully (mask: 7)
eth1: pfe0s32cc_serdes_phy serdes@44180000: Using mode 3 for SerDes subsystem
s32cc_serdes_phy serdes@44180000: Stable RX detected on XPCS1 after 0 µs
, eth2: pfe1s32cc_serdes_phy serdes@40480000: Using mode 3 for SerDes subsystem
s32cc_serdes_phy serdes@40480000: Stable RX detected on XPCS1 after 0 µs
, eth3: pfe2
Hit any key to stop autoboot:  0

setenv ethact pfe2
=> setenv ethprime pfe2
=> ping 192.168.0.1
pfe2 Waiting for PHY auto negotiation to complete......... TIMEOUT !
pfeng_netif pfe2: PHY startup failed
Enable protocol@14 failed
pfeng_netif pfe0: Clock 'rx_rgmii' enabling failed: -71
pfe1 Waiting for PHY auto negotiation to complete......... TIMEOUT !
pfeng_netif pfe1: PHY startup failed
ping failed; host 192.168.0.1 is not alive
=> mdio list
pfeng-mdio-1:
1b - Generic PHY <--> pfe1
pfeng-mdio-2:
1b - Generic PHY <--> pfe2

[alejandro_e]

Hello @khan_misbah,

Thanks for reaching out to us. Regarding your question, the SerDes configuration in U-Boot, and therefore the SGMII configuration is managed by an environment variable, the hwconfig variable, for more information please check your BSP user manual, for example for BSP44 check section 7.2.2 SerDes configuration for SGMII in U-Boot in particular page 51:

If you have already check this information, please share the following so I may be able to offer you better support:

• BSP version
• hwconfig current value

Thanks in advance

[khan_misbah]

The BSP version is 43 and the hwconfig used is:

hwconfig=serdes0:mode=xpcs0&xpcs1,clock=int,fmhz=125;xpcs0_1:speed=1G;serdes1:mode=xpcs0&xpcs1,clock=int,fmhz=125;xpcs1_1:speed=1G

[alejandro_e]

Hello @khan_misbah,

Thanks for the information. Although I am not able to use PFE2 in SGMII mode in any of my boards (or at least not directly connected to the ETH PHY), I tested the same configuration you are using with PFE1 and it seems correct.

=> printenv hwconfig
hwconfig=serdes0:mode=disabled;serdes1:mode=xpcs0&xpcs1,clock=int,fmhz=125;xpcs1_1:speed=1G

However, there are a differences in the steps we use to test, here are the commands I am using:

=> setenv ethact pfe1
=> setenv ipaddr 192.168.0.11
=> ping 192.168.0.10
Using pfe1 device
host 192.168.0.10 is alive

where 192.168.0.10 is the IP of my host machine.

Another important difference is that I am using the base device tree for ATF/U-Boot. 

Could you try with the same environment and steps I am using and share the behavior?

Thanks

[khan_misbah]

Hello,

I was also testing using the same command:

etenv ethact pfe2
=> setenv ipaddr 192.168.0.2
=> ping 192.168.0.1

as above, the IP address is already set in the uboot env variable.
The problem is in Kernel the above DTS setting works but in bootloader it does not work.

Although mdio list shows the PHY.

[alejandro_e]

Hello @khan_misbah,

Thanks for the information. Just to be completely clear, were you able to test with the default DT? My concern at the moment is that the DT fixups and your DT changes are in someway incompatible. This is because u-boot modifies the Linux DT according to the hwconfig value, and it does the same with the ATF DT (this configuration is volatile). So, I have two recommendations for now:

• Test with default ATF DT and your current value of hwconfig
• Test with your modified ATF DT and skip SerDes0 configuration in u-boot, for your setup it would be:

• serdes0:mode=xpcs0&xpcs1,clock=int,skip=boot,fmhz=125;xpcs0_1:speed=1G;serdes1:mode=xpcs0&xpcs1,clock=int,fmhz=125;xpcs1_1:speed=1G

notice the skip=boot. You can also use skip=kernel, to prevent u-boot from modifying the Kernel DT.

Please let me know if the behavior changes.

[khan_misbah]

Hello  alejandro_e

Unfortunately, both the below approach didn't worked: 

• Test with default ATF DT and your current value of hwconfig
• Test with your modified ATF DT and skip SerDes0 configuration in u-boot,
  
  
  In case of default ATF DT and current hwconfig the issue is in my h/w design we are using "TJA1104B" PHY over MDIO line, the MDC & MDIO pins are different than default in ATF as:
  

  pfe2mdioa_pins: pfe2mdioa_pins {
  pfe2mdioa_grp0 {
  pinmux = <S32CC_PINMUX(80, FUNC1)>;
  output-enable;
  slew-rate = <S32CC_FAST_SLEW_166MHZ>;
  };

  pfe2mdioa_grp1 {
  pinmux = <S32CC_PINMUX(81, FUNC2)>;
  output-enable;
  input-enable;
  slew-rate = <S32CC_FAST_SLEW_166MHZ>;
  };

  pfe2mdioa_grp2 {
  pinmux = <S32CC_PINMUX(877, FUNC2)>;
  };
  };

  In case of modified ATF DT the mdio list and mii info shows the PHY connected, but later ping gets timeout as:
  
  => mdio list
  pfeng-mdio-1:
  1b - Generic PHY <--> pfe1
  pfeng-mdio-2:
  1b - Generic PHY <--> pfe2
  =>
  => mii info
  PHY 0x1B: OUI = 0x06EC, Model = 0x03, Rev = 0x01,  10baseT, HDX
  
  

  => setenv ethprime pfe2
  => setenv ethact pfe2
  => setenv ipaddr 192.168.0.2
  => ping 192.168.0.1
  pfe2 Waiting for PHY auto negotiation to complete......... TIMEOUT !
  pfeng_netif pfe2: PHY startup failed
  Using pfe0 device

  ARP Retry count exceeded; starting again
  ping failed; host 192.168.0.1 is not alive

• The same DTS setting works in the kernel and not in u-boot in-spite of mdio list and mii info commands working.

[alejandro_e]

Hello @khan_misbah,

I understand, please allow me some time to further investigate this topic, I will get back to you with an update soon.

Thanks for your patience.

[alejandro_e]

Hello @khan_misbah,

Thanks a lot for you patience. Using your original program, with the Ethernet cable connected and after trying to ping your other device, please execute the following tests:

When compiling u-boot, change the log level to 8, in your .config file:

#
# Logging
#
CONFIG_LOG=y
CONFIG_LOG_MAX_LEVEL=8
CONFIG_LOG_DEFAULT_LEVEL=8
CONFIG_LOG_CONSOLE=y

You could even use 9, but it does not seem necessary for now.

With the modified u-boot with the logs, execute the following commands:

mii dump
mii device
net list
xpcs list
xpcs X dump
verifclk
pfeng

For the xpcs X dump, please substitute the X for each of the IDs you get in xpcs list.

Please share the complete output, including the first boot log and the command.

Thanks in advance for the information.

[khan_misbah]

 Hi alejandro_e

Please find the details u-boot log you required in the attached doc.

Regards,

Misbah

[alejandro_e]

Hello @khan_misbah,

Thanks a lot for the information. In the logs I see several errors related to the clocking, also it seems that after executing verifclk the board rebooted, without finishing the output of the command.

Is there any particular change used for your board related to clock that might be causing this issue? If possible please share the information related to clocking of the board, you can send me a private message if you prefer.

Thanks

[khan_misbah]

Hi Alejandro,

I am able to run verifclk, here is the output:

Looks like none of the Ethernet clocks are getting enabled in uboot.

mdio list
pfeng-mdio-1:
1b - Generic PHY <--> pfe1
pfeng-mdio-2:
1b - Generic PHY <--> pfe2
=> mii info
PHY 0x1B: OUI = 0x06EC, Model = 0x03, Rev = 0x01,  10baseT, HDX
=> ver
  verifclk version
=> verifclk
CMU | Monitored    | Reference | Expected            | Verified
ID  | clock        | clock     | range (MHz)         | range (MHz)
-----|--------------|-----------|---------------------|--------------------
    0|        FXOSC |      FIRC |              40.000 |              39.062
    1|         FIRC |     FXOSC |   45.600 -   50.400 |              48.080
    2|         SIRC |     FXOSC |               0.032 |               0.031
Timeout while measuring the frequency of FTM_0_REF
    3|    FTM_0_REF |     FXOSC |              40.000 |               0.000
Timeout while measuring the frequency of FTM_1_REF
    4|    FTM_1_REF |     FXOSC |              40.000 |               0.000
    5|    XBAR_DIV3 |      FIRC |             133.333 |             132.812
    6|    XBAR_M7_0 |      FIRC |             400.000 |             406.250
    7|    XBAR_DIV3 |     FXOSC |             133.333 |             132.812
    8|    XBAR_M7_1 |      FIRC |             400.000 |             406.250
    9|    XBAR_M7_2 |      FIRC |             400.000 |             406.250
   10|          PER |      FIRC |              80.000 |              78.125
   11|   SERDES_REF |     FXOSC |  100.000 -  125.000 |              99.609
   12|   FLEXRAY_PE |     FXOSC |              40.000 |    0.000 -    0.015
   13|       CAN_PE |     FXOSC |              80.000 |              47.851
   14|    GMAC_0_TX |     FXOSC |    2.500 -  125.000 |    0.000 -    0.015
   15|      GMAC_TS |     FXOSC |    5.000 -  200.000 |    0.000 -    0.015
   16|          LIN |     FXOSC |             125.000 |              62.500
   17|      QSPI_1X |     FXOSC |    0.000 -  200.000 |             199.218
   18|         SDHC |     FXOSC |             400.000 |             398.437
   20|          DDR |      FIRC |             666.666 |             812.500
   21|    GMAC_0_RX |     FXOSC |    2.500 -  125.000 |              47.851
   22|          SPI |     FXOSC |             100.000 |              47.851
   27|     A53_CORE |     FXOSC |            1000.000 |            1000.000
   28|     A53_CORE |      FIRC |            1000.000 |            1000.000
   39|      PFE_SYS |     FXOSC |             300.000 |             300.781
   46| PFE_MAC_0_TX |     FXOSC |    2.500 -  312.500 |    0.000 -    0.015
   47| PFE_MAC_0_RX |     FXOSC |    2.500 -  312.500 |              47.851
   48| PFE_MAC_1_TX |     FXOSC |    2.500 -  125.000 |    0.000 -    0.015
   49| PFE_MAC_1_RX |     FXOSC |    2.500 -  125.000 |              47.851
   50| PFE_MAC_2_TX |     FXOSC |    2.500 -  125.000 |    0.000 -    0.015
   51| PFE_MAC_2_RX |     FXOSC |    2.500 -  125.000 |              47.851

[alejandro_e]

Hello @khan_misbah,

I thanks for the information. It indeed seems that none of the Ethernet clocks are getting enabled, for example, here is the diff with my clocks, outlined in red are the important differences:

Please execute the following commands and share the output:

md 0x4033C000 0x4DF 
md 0x460A0000 0x4DF
md 0x460A4000 0x4DF
md 0x460A8000 0x4DF

The commands are just a register dump of the GMAC, PFE_EMAC0, PFE_EMAC1 and PFE_EMAC2 base addresses, the 0x4DF is the size in 32bit words.

I am attaching the output of those commands in my RDB2 board as reference. 

Please also let me know what changes did you require successfully run the verifclk command.

Thanks for all the information.

[khan_misbah]

Hello alejandro_e

The strange thing is for me is PFE2 in u-boot is not getting the clock while in kernel it is working with the same DTS setting.

In uboot the MDIO communication succeeds and both PFE1 & PFE2 PHY is detected. but during ping it gives error.

Please check the u-boot log as:

----------------------------------------------------------------------

DRAM:  3.5 GiB
Inside dm_init_and_scan............
PFE2 PHY reset
PFE1 PHY reset
GMAC0 PHY reset
PFE0 RX enable
GMAC0 RX ER
Core:  290 devices, 25 uclasses, devicetree: board
MMC:   FSL_SDHC: 0
Loading Environment from SPIFlash... SF: Detected mt35xu01gbba with page size 256 Bytes, erase size 4 KiB, total 128 MiB
*** Warning - bad CRC, using default environment

Failed to configure XPCS0_1
Failed to update XPCS1 for SerDes0
Failed to configure XPCS1_1
Failed to update XPCS1 for SerDes1
In:    serial@401c8000
Out:   serial@401c8000
Err:   serial@401c8000
Board revision: RDB2
Net:   Enable protocol@14 failed
clk_enable(clk_rx) failed: -71
eth_eqos ethernet@4033c000: Failed to start clocks (err=-71)
eqos_start_clks() failed: -71
Found PFE version 0x50300 (S32G2)
pfeng pfeng-base: Uploading CLASS firmware
pfeng pfeng-base: EMAC0 block was initialized
pfeng pfeng-base: EMAC1 block was initialized
pfeng pfeng-base: EMAC2 block was initialized
pfeng pfeng-base: Enabling the CLASS block
pfeng pfeng-base: PFE Platform started successfully (mask: 7)
eth1: pfe0s32cc_serdes_phy serdes@44180000: Using mode 3 for SerDes subsystem
s32cc_serdes_phy serdes@44180000: Stable RX detected on XPCS1 after 0 µs
, eth2: pfe1s32cc_serdes_phy serdes@40480000: Using mode 3 for SerDes subsystem
s32cc_serdes_phy serdes@40480000: Stable RX detected on XPCS1 after 0 µs
, eth3: pfe2
Hit any key to stop autoboot:  0

----------------------------------------------------------------------------------
I was expecting the hwconfig to do the clk setting in u-boot 
hwconfig=serdes0:mode=xpcs0&xpcs1,clock=int,fmhz=125;xpcs0_1:speed=1G;serdes1:mode=xpcs0&xpcs1,clock=int,fmhz=125;xpcs1_1:speed=1G

because in kernel i see the clock details as:
-----------------------------------------------------------------------
root@s32g2-vcup-platform:~# ^C
root@s32g2-vcup-platform:~# cat /sys/kernel/debug/clk/clk_summary | grep gmac0
gmac0_axi                           1       1        0        400000000   0          0     50000      Y   4033c000.ethernet               stmmaceth
gmac0_tx_mii                        1       1        0        25000000    0          0     50000      Y   4033c000.ethernet               tx_mii
gmac0_rx_mii                        1       1        0        125000000   0          0     50000      Y   4033c000.ethernet               rx_mii
gmac0_tx_rmii                       0       0        0        25000000    0          0     50000      Y   deviceless                      no_connection_id
gmac0_rx_rmii                       0       0        0        125000000   0          0     50000      Y   deviceless                      no_connection_id
gmac0_tx_rgmii                      0       0        0        25000000    0          0     50000      Y   deviceless                      no_connection_id
gmac0_rx_rgmii                      0       0        0        125000000   0          0     50000      Y   deviceless                      no_connection_id
gmac0_tx_sgmii                      0       0        0        25000000    0          0     50000      Y   deviceless                      no_connection_id
gmac0_rx_sgmii                      0       0        0        125000000   0          0     50000      Y   deviceless                      no_connection_id
gmac0_ts                            0       0        0        200000000   0          0     50000      Y   deviceless                      no_connection_id
root@s32g2-vcup-platform:~# cat /sys/kernel/debug/clk/clk_summary | grep pfe
pfe_ts                              1       1        0        200000000   0          0     50000      Y   46000000.pfe                    pfe_ts
pfe_pe                              1       1        0        600000000   0          0     50000      Y   46000000.pfe                    pfe_pe
pfe_apb                             0       0        0        300000000   0          0     50000      Y   deviceless                      no_connection_id
pfe_axi                             1       1        0        300000000   0          0     50000      Y   46000000.pfe                    pfe_sys
pfe2_tx_mii                         0       0        0        125000000   0          0     50000      Y   deviceless                      no_connection_id
pfe2_rx_mii                         0       0        0        125000000   0          0     50000      Y   deviceless                      no_connection_id
pfe2_tx_rmii                        0       0        0        125000000   0          0     50000      Y   deviceless                      no_connection_id
pfe2_rx_rmii                        0       0        0        125000000   0          0     50000      Y   deviceless                      no_connection_id
pfe2_tx_rgmii                       0       0        0        125000000   0          0     50000      Y   deviceless                      no_connection_id
pfe2_rx_rgmii                       0       0        0        125000000   0          0     50000      Y   deviceless                      no_connection_id
pfe2_tx_sgmii                       1       1        0        125000000   0          0     50000      Y   ethernet@12                     tx_sgmii
pfe2_rx_sgmii                       1       1        0        125000000   0          0     50000      Y   ethernet@12                     rx_sgmii
pfe1_tx_mii                         0       0        0        125000000   0          0     50000      Y   deviceless                      no_connection_id
pfe1_rx_mii                         0       0        0        125000000   0          0     50000      Y   deviceless                      no_connection_id
pfe1_tx_rmii                        0       0        0        125000000   0          0     50000      Y   deviceless                      no_connection_id
pfe1_rx_rmii                        0       0        0        125000000   0          0     50000      Y   deviceless                      no_connection_id
pfe1_tx_rgmii                       0       0        0        125000000   0          0     50000      Y   deviceless                      no_connection_id
pfe1_rx_rgmii                       0       0        0        125000000   0          0     50000      Y   deviceless                      no_connection_id
pfe1_tx_sgmii                       1       1        0        125000000   0          0     50000      Y   ethernet@11                     tx_sgmii
pfe1_rx_sgmii                       1       1        0        125000000   0          0     50000      Y   ethernet@11                     rx_sgmii
pfe0_tx_mii                         0       0        0        125000000   0          0     50000      Y   deviceless                      no_connection_id
pfe0_rx_mii                         0       0        0        125000000   0          0     50000      Y   deviceless                      no_connection_id
pfe0_tx_rmii                        0       0        0        125000000   0          0     50000      Y   deviceless                      no_connection_id
pfe0_rx_rmii                        0       0        0        125000000   0          0     50000      Y   deviceless                      no_connection_id
pfe0_tx_rgmii                       1       1        0        125000000   0          0     50000      Y   ethernet@10                     tx_rgmii
pfe0_rx_rgmii                       1       1        0        125000000   0          0     50000      Y   ethernet@10                     rx_rgmii
pfe0_tx_sgmii                       0       0        0        125000000   0          0     50000      Y   deviceless                      no_connection_id
pfe0_rx_sgmii                       0       0        0        125000000   0          0     50000      Y   deviceless                      no_connection_id
root@s32g2-vcup-platform:~#

______________________________________________________________

The MD command output is attached below. 

Please find the details you require as:

[alejandro_e]

Hello @khan_misbah,

Thanks for the information, I compared the registers of my PFE1 using SGMII to your PFE2, I did not find much, however, what I did find are some differences in the Clause 45 registers, and following the BSP43 manual, section 7.3.1.1 GMAC U-Boot driver and checking the S32G2-EVB3 device tree for ATF/u-boot s32g2xxa-evb3.dts#L43  (and considering that GMAC and PFE interfaces have the same registers), can you try adding the following in &pfe_mdio2:

&pfe_mdio2 {
status = "okay";

/* TJA1104B */
pfe_mdio_b_phy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <27>;
};

};

You can also try configuring the CONFIG_PHY_NXP_C45_TJA11XX to your configuration with the menuconfig in u-boot:

Which adds support for the TJA11 family.

Since I do not have your board I cannot test the exact effects of the changes, however, please test each alone and then both.

If the problem persists, please also share the output of the dm tree command in u-boot, to compare it with my own.

By the way, I do understand that it is quite unusual that Linux works and u-boot does not, however, the device tree does not define the behavior of driver, it is only a descriptor, therefore Linux and u-boot have different behaviors.

Thanks in advance.

[khan_misbah]

Hello @ alejandro_e

I made the following change in the dts:
-------------------------------------------------------

&pfe_mdio0 {
/* unused */
status = "disabled";
};

&pfe_mdio1 {
status = "okay";
/* TJA1121B */
pfe_mdio_b_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <27>;
};
};

&pfe_mdio2 {
status = "okay";
/* TJA1104B */
pfe_mdio_b_phy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <27>;
};

};

&pfe_netif0 {
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};

&pfe_netif1 {
phy-mode = "sgmii";
phy-handle = <&pfe_mdio_b_phy1>;
managed = "in-band-status";
};

&pfe_netif2 {
phy-mode = "sgmii";
phy-handle = <&pfe_mdio_b_phy2>;
managed = "in-band-status";
};
_____________________________________________
my u-boot defconfig is as:
CONFIG_ARM=y
CONFIG_ARCH_S32G2=y
CONFIG_TARGET_S32G274ARDB2=y
#CONFIG_TARGET_S32G2XXAEVB=y
CONFIG_QSPI_BOOT=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_ENV_SPI_BUS=6
CONFIG_ENV_SPI_CS=0
CONFIG_USE_DEFAULT_ENV_FILE=y
CONFIG_DEFAULT_ENV_FILE="uEnv.txt"
CONFIG_S32CC_QSPI_FREQ=133
CONFIG_SPI_FLASH_MX25UW51245G=n
#CONFIG_ENV_OFFSET_REDUND=n
CONFIG_NXP_PFENG_FW_PART="0x32c0000"
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x20000
#CONFIG_S32CC_HWCONFIG="serdes0:mode=xpcs0&xpcs1,clock=int,fmhz=125;xpcs0_1:speed=1G;serdes1:mode=xpcs0&xpcs1,clock=int,fmhz=125;xpcs1_1:speed=1G"
CONFIG_EFI_PARTITION=y
CONFIG_PHY_NXP_C45_TJA11XX=y
CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_TI_DP83869=y
CONFIG_PHY_TI=y
CONFIG_PHY_TI_GENERIC=y
#CONFIG_LOG=y
#CONFIG_LOG_MAX_LEVEL=8
#CONFIG_LOG_DEFAULT_LEVEL=8
#CONFIG_LOG_CONSOLE=y

-----------------------------------------------------------------
Why MDIO list is still detecting it as Generic PHY ?
=> mdio list
pfeng-mdio-1:
1b - Generic PHY <--> pfe1
pfeng-mdio-2:
1b - Generic PHY <--> pfe2

output of "dm tree" command is as attached.

[alejandro_e]

Hello @khan_misbah,

Thanks again for the information. Given the extended and complexity of this ticket I will raise this topic with the internal team for better support. Fortunately I have gather a lot of information regarding your setup, I will share all of that with them for a better analysis.

I will get back to you once I have relevant updates.

Thanks

[khan_misbah]

Hello @alejandro_e,

We need some solution; we are running out of time. 
Kindly help in resolving the issue.

[alejandro_e]

Hello @khan_misbah,

I understand this is a critical topic for you. However with the current information I can only see the clock problem but not its root cause. Can you share more details regarding the clock configuration of your board and your device tree? For example, I did not completely understand the changes you performed for the verifclk command to run correctly.

You can send me your schematics and full kernel repo for example, so I may compare it with the schematics of the RDB2 and the S32G2 BSP Linux respectively. You can use the private feature of the community or the support tickets in the NXP page, in the second case you can mention this post's link and my username to ensure it is assigned to me.

Thanks

[alejandro_e]

Hello @khan_misbah,

I have finally received a reply from the internal team. They are requesting the following:

• Complete Linux bootlogs, you can either get them from the terminal or using the dmesg command
• Complete u-boot/ATF and Linux device tree files. 

As mentioned before, you can use the private message functionality of this community or you can open a private support ticket and add the link to this post so I know it is related.

Thanks for the information and sorry for the late reply.

[khan_misbah]

Hi @alejandro_e 

Please find the private chat case no "00740646" that i created.